Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10)

CIC: async→sync reset on decimation control, valid pipeline, and comb
section. Added (* use_dsp = "yes" *) on comb[] to force DSP48E1
absorption of 28-bit subtracts (was 7-deep CARRY4, Build 9 critical
path at WNS +0.128ns). Targets ~10 additional DSP48E1s.

FIR: async→sync reset on delay_line block, enabling DSP48E1 AREG/BREG
absorption. Targets elimination of ~2,522 DPIR-1 methodology warnings.

13/13 regression suites pass. Integration golden: 2048/2048 exact match.

9_Firmware/9_2_FPGA/fir_lowpass.v

@@ -92,8 +92,13 @@ integer i;
 
 // ============================================================================
 // Pipeline Stage 0: Shift delay line on data_valid
+// Sync reset: enables DSP48E1 AREG/BREG absorption for delay_line registers
+// feeding the multipliers. Async reset (FDCE) prevented Vivado from using
+// the DSP48E1 internal A/B pipeline registers — the source of 2,522 DPIR-1
+// methodology warnings in Build 9. Converting to sync reset (FDRE) allows
+// Vivado to absorb these into DSP48E1 AREG/BREG, further reducing LUT count.
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         for (i = 0; i < TAPS; i = i + 1) begin
             delay_line[i] <= 0;