fix: align all range/carrier/velocity values to PLFM hardware + FPGA bug fixes

- Correct carrier from 10.525/10 GHz to 10.5 GHz (verified ADF4382 config)
- Correct range-per-bin from 4.8/5.6/781.25 m to 24.0 m (matched-filter)
- Correct velocity resolution from 1.484 to 2.67 m/s/bin (PRI-based)
- Correct processing rate from 4 MSPS to 100 MSPS (post-DDC)
- Correct max range from 307/5000/50000 m to 1536 m (64 bins x 24 m)
- Add WaveformConfig.pri_s field (167 us PRI for velocity calculation)
- Fix short chirp chirp_complete deadlock (Bug A)
- Remove dead short_chirp ports, rename long_chirp to ref_chirp (Bug B)
- Fix stale latency comment 2159 -> 3187 cycles (Bug C)
- Create radar_params.vh as single source of truth for FPGA parameters
- Lower RadarSettings.cpp map_size validation bound from 1000 to 100
- Add PLFM hardware constants to golden_reference.py
- Update all GUI versions, tests, and cross-layer contracts

All 244 tests passing (167 Python + 21 MCU + 29 cross-layer + 27 FPGA)

9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py

@@ -2,8 +2,8 @@
 """
 golden_reference.py — AERIS-10 FPGA bit-accurate golden reference model
 
-Uses ADI CN0566 Phaser radar data (10.525 GHz X-band FMCW) to validate
-the FPGA signal processing pipeline stage by stage:
+Uses ADI CN0566 Phaser radar data (10.525 GHz, used as test stimulus only) to
+validate the FPGA signal processing pipeline stage by stage:
 
     ADC → DDC (NCO+mixer+CIC+FIR) → Range FFT → Doppler FFT → Detection
 
@@ -90,7 +90,8 @@ HAMMING_Q15 = [
     0x3088, 0x1B6D, 0x0E5C, 0x0A3D,
 ]
 
-# ADI dataset parameters
+# ADI dataset parameters — used ONLY for loading/requantizing ADI Phaser test data.
+# These are NOT PLFM hardware parameters. See AERIS-10 constants below.
 ADI_SAMPLE_RATE = 4e6            # 4 MSPS
 ADI_IF_FREQ = 100e3             # 100 kHz IF
 ADI_RF_FREQ = 9.9e9             # 9.9 GHz
@@ -99,9 +100,17 @@ ADI_RAMP_TIME = 300e-6          # 300 us
 ADI_NUM_CHIRPS = 256
 ADI_SAMPLES_PER_CHIRP = 1079
 
-# AERIS-10 parameters
-AERIS_FS = 400e6                 # 400 MHz ADC clock
-AERIS_IF = 120e6                 # 120 MHz IF
+# AERIS-10 hardware parameters (from ADF4382/AD9523/main.cpp configuration)
+AERIS_FS = 400e6                 # 400 MHz ADC clock (AD9523 OUT4)
+AERIS_IF = 120e6                 # 120 MHz IF (TX 10.5 GHz - RX 10.38 GHz)
+AERIS_FS_PROCESSING = 100e6     # Post-DDC rate (400 MSPS / 4x CIC)
+AERIS_CARRIER_HZ = 10.5e9       # TX LO (ADF4382, verified)
+AERIS_RX_LO_HZ = 10.38e9        # RX LO (ADF4382)
+AERIS_CHIRP_BW = 20e6           # Chirp bandwidth (target: 30 MHz Phase 1)
+AERIS_LONG_CHIRP_S = 30e-6      # Long chirp duration
+AERIS_PRI_S = 167e-6            # Pulse repetition interval
+AERIS_DECIMATION = 16           # Range bin decimation (1024 → 64)
+AERIS_RANGE_PER_BIN = 24.0      # Meters per decimated bin
 
 
 # ===========================================================================

9_Firmware/9_2_FPGA/tb/cosim/validate_mem_files.py

@@ -421,13 +421,13 @@ def test_latency_buffer():
     #
     # For synthesis: the latency_buffer feeds ref data to the chain via
     # chirp_memory_loader_param → latency_buffer → chain.
-    # But wait — looking at radar_receiver_final.v:
+    # Looking at radar_receiver_final.v:
     #   - mem_request drives valid_in on the latency buffer
     #   - The buffer delays {ref_i, ref_q} by LATENCY valid_in cycles
-    #   - The delayed output feeds long_chirp_real/imag → chain
+    #   - The delayed output feeds ref_chirp_real/imag → chain
     #
     # The purpose: the chain in the SYNTHESIS branch reads reference data
-    # via the long_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
+    # via the ref_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
     # input samples). The reference data needs to arrive LATENCY cycles
     # after the first mem_request, where LATENCY accounts for:
     #   - The fft_engine pipeline latency from input to output