feat: Phase C co-sim tests + Doppler compare wired into CI
- Add 15 Tier 5 pipeline co-sim tests (cross-layer): decimator, MTI, Doppler, DC notch, CFAR, and full-chain golden match - Add 4 SoftwareFPGA tests (test_v7): golden fixture integrity, process_chirps wiring validation against manual chain - Wire compare_doppler.py into run_regression.sh with 3 scenarios (stationary, moving, two_targets) replacing single unvalidated run - Harden _load_npy to raise on missing files; expand sentinel check to all 14 golden artifacts - DC notch test verifies both zero and pass-through bins Test counts: 172 python + 55 cross-layer + 21 MCU + 29 FPGA = 277 total
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Jason
@@ -666,6 +666,231 @@ class TestSoftwareFPGASignalChain(unittest.TestCase):
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self.assertEqual(frame_cfar.magnitude.shape, (64, 32))
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class TestGoldenReferenceReplayFixtures(unittest.TestCase):
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"""Golden replay fixtures and SoftwareFPGA smoke tests.
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Phase C3 adds two fixture-integrity tests that verify the committed
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`golden_reference.py` pipeline still reproduces the checked-in `.npy`
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artifacts, plus one `SoftwareFPGA.process_chirps()` smoke test that checks
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the GUI replay path still produces a valid `RadarFrame` shape.
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"""
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COSIM_DIR = os.path.join(
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os.path.dirname(__file__), "..", "9_2_FPGA", "tb", "cosim",
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"real_data", "hex"
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)
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REQUIRED_COSIM_FILES = (
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"range_fft_all_i.npy",
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"range_fft_all_q.npy",
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"decimated_range_i.npy",
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"decimated_range_q.npy",
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"fullchain_cfar_flags.npy",
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"fullchain_cfar_mag.npy",
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)
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def _cosim_available(self):
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return all(
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os.path.isfile(os.path.join(self.COSIM_DIR, name))
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for name in self.REQUIRED_COSIM_FILES
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)
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def _load(self, name):
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return np.load(os.path.join(self.COSIM_DIR, name))
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def test_decimator_matches_golden(self):
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"""Golden decimator helper must reproduce committed decimated output."""
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if not self._cosim_available():
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self.skipTest("co-sim data not found")
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import sys as _sys
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from pathlib import Path as _Path
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_gr_dir = str(
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_Path(__file__).resolve().parents[1]
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/ "9_2_FPGA" / "tb" / "cosim" / "real_data"
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)
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if _gr_dir not in _sys.path:
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_sys.path.insert(0, _gr_dir)
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from golden_reference import run_range_bin_decimator
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range_i = self._load("range_fft_all_i.npy")
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range_q = self._load("range_fft_all_q.npy")
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expected_i = self._load("decimated_range_i.npy")
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expected_q = self._load("decimated_range_q.npy")
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got_i, got_q = run_range_bin_decimator(range_i, range_q)
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np.testing.assert_array_equal(
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got_i,
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expected_i,
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err_msg="Golden decimator I drifted from committed fixture",
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)
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np.testing.assert_array_equal(
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got_q,
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expected_q,
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err_msg="Golden decimator Q drifted from committed fixture",
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)
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def test_full_chain_cfar_output_matches_golden(self):
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"""Golden full pipeline must reproduce committed CFAR golden data."""
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if not self._cosim_available():
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self.skipTest("co-sim data not found")
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import sys as _sys
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from pathlib import Path as _Path
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_gr_dir = str(
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_Path(__file__).resolve().parents[1]
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/ "9_2_FPGA" / "tb" / "cosim" / "real_data"
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)
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if _gr_dir not in _sys.path:
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_sys.path.insert(0, _gr_dir)
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from golden_reference import (
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run_range_bin_decimator, run_mti_canceller,
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run_doppler_fft, run_dc_notch, run_cfar_ca,
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)
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range_i = self._load("range_fft_all_i.npy")
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range_q = self._load("range_fft_all_q.npy")
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expected_flags = self._load("fullchain_cfar_flags.npy")
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expected_mag = self._load("fullchain_cfar_mag.npy")
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# Run the same chain as golden_reference.py:main()
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twiddle_16 = os.path.join(
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os.path.dirname(__file__), "..", "9_2_FPGA",
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"fft_twiddle_16.mem",
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)
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if not os.path.exists(twiddle_16):
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self.skipTest("fft_twiddle_16.mem not found")
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dec_i, dec_q = run_range_bin_decimator(range_i, range_q)
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mti_i, mti_q = run_mti_canceller(dec_i, dec_q, enable=True)
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dop_i, dop_q = run_doppler_fft(
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mti_i, mti_q, twiddle_file_16=twiddle_16,
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)
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notch_i, notch_q = run_dc_notch(dop_i, dop_q, width=2)
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flags, mag, _thr = run_cfar_ca(
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notch_i, notch_q, guard=2, train=8, alpha_q44=0x30, mode="CA",
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)
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np.testing.assert_array_equal(
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flags,
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expected_flags,
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err_msg="Golden full-chain CFAR flags mismatch committed fixture",
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)
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np.testing.assert_array_equal(
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mag,
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expected_mag,
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err_msg="Golden full-chain CFAR magnitudes mismatch committed fixture",
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)
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def test_software_fpga_frame_shape_from_range_fft(self):
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"""SoftwareFPGA.process_chirps on range_fft data produces correct shape.
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NOTE: process_chirps re-runs the range FFT, so we can't feed it
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post-FFT data and expect golden match. This test verifies that the
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RadarFrame output has the right shape and that the chain doesn't crash
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when given realistic-amplitude input.
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"""
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if not self._cosim_available():
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self.skipTest("co-sim data not found")
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from v7.software_fpga import SoftwareFPGA
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from radar_protocol import RadarFrame
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# Use decimated data padded to 1024 as input (so range FFT has content)
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dec_i = self._load("decimated_range_i.npy")
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dec_q = self._load("decimated_range_q.npy")
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iq_i = np.zeros((32, 1024), dtype=np.int64)
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iq_q = np.zeros((32, 1024), dtype=np.int64)
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iq_i[:, :dec_i.shape[1]] = dec_i
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iq_q[:, :dec_q.shape[1]] = dec_q
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fpga = SoftwareFPGA()
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fpga.set_mti_enable(True)
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fpga.set_cfar_enable(True)
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fpga.set_dc_notch_width(2)
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frame = fpga.process_chirps(iq_i, iq_q, frame_number=99)
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self.assertIsInstance(frame, RadarFrame)
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self.assertEqual(frame.range_doppler_i.shape, (64, 32))
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self.assertEqual(frame.magnitude.shape, (64, 32))
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self.assertEqual(frame.detections.shape, (64, 32))
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self.assertEqual(frame.range_profile.shape, (64,))
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self.assertEqual(frame.frame_number, 99)
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def test_software_fpga_wiring_matches_manual_chain(self):
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"""SoftwareFPGA.process_chirps must call stages in the correct order
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with the correct parameters.
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Feeds identical synthetic IQ through both SoftwareFPGA and a manual
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golden_reference chain, then asserts the CFAR output matches.
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This catches wiring bugs: wrong stage order, wrong default params,
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missing DC notch, etc.
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"""
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from v7.software_fpga import SoftwareFPGA, TWIDDLE_1024, TWIDDLE_16
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if not os.path.exists(TWIDDLE_1024) or not os.path.exists(TWIDDLE_16):
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self.skipTest("twiddle files not found")
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import sys as _sys
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from pathlib import Path as _Path
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_gr_dir = str(
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_Path(__file__).resolve().parents[1]
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/ "9_2_FPGA" / "tb" / "cosim" / "real_data"
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)
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if _gr_dir not in _sys.path:
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_sys.path.insert(0, _gr_dir)
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from golden_reference import (
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run_range_fft, run_range_bin_decimator, run_mti_canceller,
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run_doppler_fft, run_dc_notch, run_cfar_ca,
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)
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# Deterministic synthetic input — small int16 values to avoid overflow
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rng = np.random.RandomState(42)
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iq_i = rng.randint(-500, 500, size=(32, 1024), dtype=np.int64)
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iq_q = rng.randint(-500, 500, size=(32, 1024), dtype=np.int64)
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# --- SoftwareFPGA path (what we're testing) ---
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fpga = SoftwareFPGA()
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fpga.set_mti_enable(True)
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fpga.set_cfar_enable(True)
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fpga.set_dc_notch_width(2)
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frame = fpga.process_chirps(iq_i.copy(), iq_q.copy(), frame_number=0)
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# --- Manual golden_reference chain (ground truth) ---
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range_i = np.zeros_like(iq_i)
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range_q = np.zeros_like(iq_q)
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for c in range(32):
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range_i[c], range_q[c] = run_range_fft(
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iq_i[c], iq_q[c], twiddle_file=TWIDDLE_1024,
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)
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dec_i, dec_q = run_range_bin_decimator(range_i, range_q)
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mti_i, mti_q = run_mti_canceller(dec_i, dec_q, enable=True)
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dop_i, dop_q = run_doppler_fft(
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mti_i, mti_q, twiddle_file_16=TWIDDLE_16,
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)
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notch_i, notch_q = run_dc_notch(dop_i, dop_q, width=2)
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flags, mag, _thr = run_cfar_ca(
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notch_i, notch_q, guard=2, train=8, alpha_q44=0x30, mode="CA",
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)
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# --- Compare ---
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np.testing.assert_array_equal(
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frame.detections, flags.astype(np.uint8),
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err_msg="SoftwareFPGA CFAR flags differ from manual chain",
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)
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np.testing.assert_array_equal(
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frame.magnitude, mag.astype(np.float64),
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err_msg="SoftwareFPGA CFAR magnitudes differ from manual chain",
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)
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expected_rd_i = np.clip(notch_i, -32768, 32767).astype(np.int16)
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expected_rd_q = np.clip(notch_q, -32768, 32767).astype(np.int16)
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np.testing.assert_array_equal(
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frame.range_doppler_i, expected_rd_i,
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err_msg="SoftwareFPGA range_doppler_i differs from manual chain",
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)
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np.testing.assert_array_equal(
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frame.range_doppler_q, expected_rd_q,
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err_msg="SoftwareFPGA range_doppler_q differs from manual chain",
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)
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class TestQuantizeRawIQ(unittest.TestCase):
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"""quantize_raw_iq utility function."""
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