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Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

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Phase 0+ timing optimization (attempts #13-22 + implementation):

NCO (nco_400m_enhanced.v):
- 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX
- DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain)
- Registered phase_inc_dithered to break cascaded 32-bit add path

DDC (ddc_400m.v):
- Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1)
- CEP=1, RSTP=!reset_n for proper pipeline control
- 3-stage dsp_valid_pipe for PREG=1 latency
- Behavioral sim model under ifdef SIMULATION for Icarus compatibility

CIC (cic_decimator_4x_enhanced.v):
- 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28
- Removed integrator/comb saturation (CIC uses wrapping arithmetic by design)
- Pipelined output saturation comparison

CDC/ASYNC_REG:
- ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v,
  radar_system_top.v, usb_data_interface.v)
- Sync reset in generate blocks (cdc_modules.v)

Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints,
850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t.
All testbenches pass: 241/244 (3 known stub failures).
This commit is contained in:
Jason
2026-03-16 01:02:07 +02:00
parent 1e51b739a7
commit c983a3c705
15 changed files with 5883 additions and 5466 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/cdc_modules.v
+19 -20
View File
@@ -2,6 +2,9 @@
// ============================================================================ // ============================================================================
// CDC FOR MULTI-BIT DATA (ADVANCED) // CDC FOR MULTI-BIT DATA (ADVANCED)
// Uses Gray-code encoding with synchronous reset on sync chain to avoid
// latch inference. ASYNC_REG attributes ensure Vivado places synchronizer
// FFs in the same slice for optimal MTBF.
// ============================================================================ // ============================================================================
module cdc_adc_to_processing #( module cdc_adc_to_processing #(
parameter WIDTH = 8, parameter WIDTH = 8,
@@ -38,15 +41,16 @@ module cdc_adc_to_processing #(
// Source domain registers // Source domain registers
reg [WIDTH-1:0] src_data_reg; reg [WIDTH-1:0] src_data_reg;
reg [1:0] src_toggle = 2'b00; reg [1:0] src_toggle = 2'b00;
reg src_toggle_sync = 0;
// Destination domain registers // Destination domain synchronizer registers
reg [WIDTH-1:0] dst_data_gray [0:STAGES-1]; // ASYNC_REG on memory arrays applies to all elements
reg [1:0] dst_toggle_sync [0:STAGES-1]; (* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] dst_data_gray [0:STAGES-1];
(* ASYNC_REG = "TRUE" *) reg [1:0] dst_toggle_sync [0:STAGES-1];
reg [WIDTH-1:0] dst_data_reg; reg [WIDTH-1:0] dst_data_reg;
reg dst_valid_reg = 0; reg dst_valid_reg = 0;
reg [1:0] prev_dst_toggle = 2'b00; reg [1:0] prev_dst_toggle = 2'b00;
// Source domain: capture data and toggle
always @(posedge src_clk or negedge reset_n) begin always @(posedge src_clk or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
src_data_reg <= 0; src_data_reg <= 0;
@@ -57,17 +61,16 @@ module cdc_adc_to_processing #(
end end
end end
// CDC synchronization chain for data // CDC synchronization chain for data — SYNCHRONOUS RESET
// Using synchronous reset avoids latch inference in Vivado.
// For CDC synchronizers, synchronous reset is preferred because
// the reset value is sampled safely within the clock domain.
genvar i; genvar i;
generate generate
for (i = 0; i < STAGES; i = i + 1) begin : data_sync_chain for (i = 0; i < STAGES; i = i + 1) begin : data_sync_chain
always @(posedge dst_clk or negedge reset_n) begin always @(posedge dst_clk) begin
if (!reset_n) begin if (!reset_n) begin
if (i == 0) begin dst_data_gray[i] <= 0;
dst_data_gray[i] <= 0;
end else begin
dst_data_gray[i] <= dst_data_gray[i-1];
end
end else begin end else begin
if (i == 0) begin if (i == 0) begin
// Convert to gray code at domain crossing // Convert to gray code at domain crossing
@@ -80,13 +83,9 @@ module cdc_adc_to_processing #(
end end
for (i = 0; i < STAGES; i = i + 1) begin : toggle_sync_chain for (i = 0; i < STAGES; i = i + 1) begin : toggle_sync_chain
always @(posedge dst_clk or negedge reset_n) begin always @(posedge dst_clk) begin
if (!reset_n) begin if (!reset_n) begin
if (i == 0) begin dst_toggle_sync[i] <= 2'b00;
dst_toggle_sync[i] <= 2'b00;
end else begin
dst_toggle_sync[i] <= dst_toggle_sync[i-1];
end
end else begin end else begin
if (i == 0) begin if (i == 0) begin
dst_toggle_sync[i] <= src_toggle; dst_toggle_sync[i] <= src_toggle;
@@ -136,7 +135,7 @@ module cdc_single_bit #(
output wire dst_signal output wire dst_signal
); );
reg [STAGES-1:0] sync_chain; (* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] sync_chain;
always @(posedge dst_clk or negedge reset_n) begin always @(posedge dst_clk or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
@@ -171,13 +170,13 @@ module cdc_handshake #(
reg [WIDTH-1:0] src_data_reg; reg [WIDTH-1:0] src_data_reg;
reg src_busy = 0; reg src_busy = 0;
reg src_ack_sync = 0; reg src_ack_sync = 0;
reg [1:0] src_ack_sync_chain = 2'b00; (* ASYNC_REG = "TRUE" *) reg [1:0] src_ack_sync_chain = 2'b00;
// Destination domain // Destination domain
reg [WIDTH-1:0] dst_data_reg; reg [WIDTH-1:0] dst_data_reg;
reg dst_valid_reg = 0; reg dst_valid_reg = 0;
reg dst_req_sync = 0; reg dst_req_sync = 0;
reg [1:0] dst_req_sync_chain = 2'b00; (* ASYNC_REG = "TRUE" *) reg [1:0] dst_req_sync_chain = 2'b00;
reg dst_ack = 0; reg dst_ack = 0;
// Source clock domain // Source clock domain
9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+53 -79
View File
@@ -15,17 +15,20 @@ parameter STAGES = 5;
parameter DECIMATION = 4; parameter DECIMATION = 4;
parameter COMB_DELAY = 1; parameter COMB_DELAY = 1;
// Increased bit width for 18-bit input with headroom // Accumulator width: input_width + N*log2(R) = 18 + 5*2 = 28 bits
reg signed [35:0] integrator [0:STAGES-1]; // 36-bit for better dynamic range // (36-bit was over-provisioned; 28 bits is mathematically exact for R=4, N=5)
reg signed [35:0] comb [0:STAGES-1]; localparam ACC_WIDTH = 28;
reg signed [35:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
reg signed [ACC_WIDTH-1:0] integrator [0:STAGES-1];
reg signed [ACC_WIDTH-1:0] comb [0:STAGES-1];
reg signed [ACC_WIDTH-1:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
// Enhanced control and monitoring // Enhanced control and monitoring
reg [1:0] decimation_counter; reg [1:0] decimation_counter;
reg data_valid_delayed; reg data_valid_delayed;
reg data_valid_comb; reg data_valid_comb;
reg [7:0] output_counter; reg [7:0] output_counter;
reg [35:0] max_integrator_value; reg [ACC_WIDTH-1:0] max_integrator_value;
reg overflow_detected; reg overflow_detected;
reg overflow_latched; // Latched overflow indicator reg overflow_latched; // Latched overflow indicator
@@ -39,10 +42,16 @@ reg comb_saturation_detected;
reg [7:0] comb_saturation_event_count; reg [7:0] comb_saturation_event_count;
// Temporary signals for calculations // Temporary signals for calculations
reg signed [35:0] abs_integrator_value; reg signed [ACC_WIDTH-1:0] abs_integrator_value;
reg signed [35:0] temp_scaled_output; reg signed [ACC_WIDTH-1:0] temp_scaled_output;
reg signed [17:0] temp_output; // Temporary output for proper range checking reg signed [17:0] temp_output; // Temporary output for proper range checking
// Pipeline stage for saturation comparison — breaks CARRY4 chain from timing path
reg sat_pos; // temp_scaled_output > 131071 (registered)
reg sat_neg; // temp_scaled_output < -131072 (registered)
reg signed [17:0] temp_output_pipe; // Registered passthrough value
reg data_out_valid_pipe; // Delayed valid for pipelined output
integer i, j; integer i, j;
// Initialize // Initialize
@@ -70,6 +79,10 @@ initial begin
abs_integrator_value = 0; abs_integrator_value = 0;
temp_scaled_output = 0; temp_scaled_output = 0;
temp_output = 0; temp_output = 0;
sat_pos = 0;
sat_neg = 0;
temp_output_pipe = 0;
data_out_valid_pipe = 0;
comb_overflow_latched = 0; comb_overflow_latched = 0;
comb_saturation_detected = 0; comb_saturation_detected = 0;
comb_saturation_event_count = 0; comb_saturation_event_count = 0;
@@ -106,54 +119,23 @@ always @(posedge clk or negedge reset_n) begin
if (data_valid) begin if (data_valid) begin
sample_count <= sample_count + 1; sample_count <= sample_count + 1;
// First integrator stage with enhanced saturation detection // Integrator stages — standard CIC uses wrapping (modular) arithmetic.
if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) > (2**35 - 1)) begin // Saturation clamping is removed because CIC math relies on wrap-around;
integrator[0] <= (2**35 - 1); // the comb stages difference successive integrator values, canceling wraps.
overflow_detected <= 1'b1; integrator[0] <= integrator[0] + {{(ACC_WIDTH-18){data_in[17]}}, data_in};
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_SATURATION: Positive overflow at sample %0d", sample_count);
`endif
end else if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) < -(2**35)) begin
integrator[0] <= -(2**35);
overflow_detected <= 1'b1;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_SATURATION: Negative overflow at sample %0d", sample_count);
`endif
end else begin
integrator[0] <= integrator[0] + $signed({{18{data_in[17]}}, data_in});
overflow_detected <= 1'b0; // Only clear immediate detection, not latched
end
// Calculate absolute value for monitoring // Calculate absolute value for monitoring
abs_integrator_value <= (integrator[0][35]) ? -integrator[0] : integrator[0]; abs_integrator_value <= (integrator[0][ACC_WIDTH-1]) ? -integrator[0] : integrator[0];
// Track maximum integrator value for gain monitoring (absolute value) // Track maximum integrator value for gain monitoring (absolute value)
if (abs_integrator_value > max_integrator_value) begin if (abs_integrator_value > max_integrator_value) begin
max_integrator_value <= abs_integrator_value; max_integrator_value <= abs_integrator_value;
max_value_monitor <= abs_integrator_value[31:24]; max_value_monitor <= abs_integrator_value[ACC_WIDTH-5:ACC_WIDTH-12];
end end
// Remaining integrator stages with saturation protection // Remaining integrator stages — pure accumulation, no saturation
for (i = 1; i < STAGES; i = i + 1) begin for (i = 1; i < STAGES; i = i + 1) begin
if (integrator[i] + integrator[i-1] > (2**35 - 1)) begin integrator[i] <= integrator[i] + integrator[i-1];
integrator[i] <= (2**35 - 1);
overflow_detected <= 1'b1;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
end else if (integrator[i] + integrator[i-1] < -(2**35)) begin
integrator[i] <= -(2**35);
overflow_detected <= 1'b1;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
end else begin
integrator[i] <= integrator[i] + integrator[i-1];
end
end end
// Enhanced decimation control // Enhanced decimation control
@@ -194,6 +176,10 @@ always @(posedge clk or negedge reset_n) begin
data_out_valid <= 0; data_out_valid <= 0;
temp_scaled_output <= 0; temp_scaled_output <= 0;
temp_output <= 0; temp_output <= 0;
sat_pos <= 0;
sat_neg <= 0;
temp_output_pipe <= 0;
data_out_valid_pipe <= 0;
comb_overflow_latched <= 0; comb_overflow_latched <= 0;
comb_saturation_detected <= 0; comb_saturation_detected <= 0;
comb_saturation_event_count <= 0; comb_saturation_event_count <= 0;
@@ -207,21 +193,11 @@ always @(posedge clk or negedge reset_n) begin
end end
if (data_valid_comb) begin if (data_valid_comb) begin
// Enhanced comb processing with saturation check // Comb processing — raw subtraction only (no saturation check needed;
// comb is a differencing stage, cannot overflow if integrators are bounded)
for (i = 0; i < STAGES; i = i + 1) begin for (i = 0; i < STAGES; i = i + 1) begin
if (i == 0) begin if (i == 0) begin
// Check for comb stage saturation comb[0] <= integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1];
if (integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1] > (2**35 - 1)) begin
comb[0] <= (2**35 - 1);
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else if (integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1] < -(2**35)) begin
comb[0] <= -(2**35);
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else begin
comb[0] <= integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1];
end
// Update delay line for first stage // Update delay line for first stage
for (j = COMB_DELAY-1; j > 0; j = j - 1) begin for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
@@ -229,18 +205,7 @@ always @(posedge clk or negedge reset_n) begin
end end
comb_delay[0][0] <= integrator[STAGES-1]; comb_delay[0][0] <= integrator[STAGES-1];
end else begin end else begin
// Check for comb stage saturation comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
if (comb[i-1] - comb_delay[i][COMB_DELAY-1] > (2**35 - 1)) begin
comb[i] <= (2**35 - 1);
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else if (comb[i-1] - comb_delay[i][COMB_DELAY-1] < -(2**35)) begin
comb[i] <= -(2**35);
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else begin
comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
end
// Update delay line // Update delay line
for (j = COMB_DELAY-1; j > 0; j = j - 1) begin for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
@@ -257,27 +222,36 @@ always @(posedge clk or negedge reset_n) begin
// FIXED: Extract 18-bit output properly // FIXED: Extract 18-bit output properly
temp_output <= temp_scaled_output[17:0]; temp_output <= temp_scaled_output[17:0];
// FIXED: Proper saturation detection for 18-bit signed range // Pipeline Stage 2: Register saturation comparison flags
if (temp_scaled_output > 131071) begin // 2^17 - 1 // This breaks the CARRY4 chain out of the data_out critical path
sat_pos <= (temp_scaled_output > 131071);
sat_neg <= (temp_scaled_output < -131072);
temp_output_pipe <= temp_scaled_output[17:0];
data_out_valid_pipe <= 1;
end else begin
data_out_valid_pipe <= 0;
end
// Pipeline Stage 3: MUX from registered comparison flags
if (data_out_valid_pipe) begin
if (sat_pos) begin
data_out <= 131071; data_out <= 131071;
comb_overflow_latched <= 1'b1; comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1; comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1; comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION `ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Positive saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d", $display("CIC_OUTPUT_SAT: TRUE Positive saturation, final_out=%d", 131071);
comb[STAGES-1], temp_scaled_output, temp_output, 131071);
`endif `endif
end else if (temp_scaled_output < -131072) begin // -2^17 end else if (sat_neg) begin
data_out <= -131072; data_out <= -131072;
comb_overflow_latched <= 1'b1; comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1; comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1; comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION `ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Negative saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d", $display("CIC_OUTPUT_SAT: TRUE Negative saturation, final_out=%d", -131072);
comb[STAGES-1], temp_scaled_output, temp_output, -131072);
`endif `endif
end else begin end else begin
data_out <= temp_output; data_out <= temp_output_pipe;
comb_overflow_latched <= 1'b0; comb_overflow_latched <= 1'b0;
comb_saturation_detected <= 1'b0; comb_saturation_detected <= 1'b0;
end end
9_Firmware/9_2_FPGA/ddc_400m.v
+295 -38
View File
@@ -54,9 +54,13 @@ reg [2:0] saturation_count;
reg overflow_detected; reg overflow_detected;
reg [7:0] error_counter; reg [7:0] error_counter;
// CDC synchronization for control signals // CDC synchronization for control signals (2-stage synchronizers)
reg mixers_enable_sync; (* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
reg bypass_mode_sync; (* ASYNC_REG = "TRUE" *) reg [1:0] bypass_mode_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
wire mixers_enable_sync;
wire bypass_mode_sync;
wire force_saturation_sync;
// Debug monitoring signals // Debug monitoring signals
reg [31:0] sample_counter; reg [31:0] sample_counter;
@@ -66,14 +70,15 @@ wire signed [17:0] debug_mixed_q_trunc;
// Real-time status monitoring // Real-time status monitoring
reg [7:0] signal_power_i, signal_power_q; reg [7:0] signal_power_i, signal_power_q;
// Enhanced saturation injection for testing
reg force_saturation_sync;
// Internal mixing signals // Internal mixing signals
reg signed [MIXER_WIDTH-1:0] adc_signed; // DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 handles all internal pipelining
// Latency: 3 cycles (1 for AREG/BREG, 1 for MREG, 1 for PREG)
wire signed [MIXER_WIDTH-1:0] adc_signed_w;
reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q; reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q;
reg mixed_valid; reg mixed_valid;
reg mixer_overflow_i, mixer_overflow_q; reg mixer_overflow_i, mixer_overflow_q;
// Pipeline valid tracking: 3-stage shift register to match DSP48E1 AREG+MREG+PREG latency
reg [2:0] dsp_valid_pipe;
// Output stage registers // Output stage registers
reg signed [17:0] baseband_i_reg, baseband_q_reg; reg signed [17:0] baseband_i_reg, baseband_q_reg;
@@ -83,7 +88,7 @@ reg baseband_valid_reg;
// Phase Dithering Signals // Phase Dithering Signals
// ============================================================================ // ============================================================================
wire [7:0] phase_dither_bits; wire [7:0] phase_dither_bits;
wire [31:0] phase_inc_dithered; reg [31:0] phase_inc_dithered;
@@ -97,17 +102,21 @@ assign debug_mixed_i_trunc = mixed_i[25:8];
assign debug_mixed_q_trunc = mixed_q[25:8]; assign debug_mixed_q_trunc = mixed_q[25:8];
// ============================================================================ // ============================================================================
// Clock Domain Crossing for Control Signals // Clock Domain Crossing for Control Signals (2-stage synchronizers)
// ============================================================================ // ============================================================================
assign mixers_enable_sync = mixers_enable_sync_chain[1];
assign bypass_mode_sync = bypass_mode_sync_chain[1];
assign force_saturation_sync = force_saturation_sync_chain[1];
always @(posedge clk_400m or negedge reset_n) begin always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
mixers_enable_sync <= 1'b0; mixers_enable_sync_chain <= 2'b00;
bypass_mode_sync <= 1'b0; bypass_mode_sync_chain <= 2'b00;
force_saturation_sync <= 1'b0; force_saturation_sync_chain <= 2'b00;
end else begin end else begin
mixers_enable_sync <= mixers_enable; mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
bypass_mode_sync <= bypass_mode; bypass_mode_sync_chain <= {bypass_mode_sync_chain[0], bypass_mode};
force_saturation_sync <= force_saturation; force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
end end
end end
@@ -117,7 +126,6 @@ end
always @(posedge clk_400m or negedge reset_n) begin always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n || reset_monitors) begin if (!reset_n || reset_monitors) begin
sample_counter <= 0; sample_counter <= 0;
saturation_count <= 0;
error_counter <= 0; error_counter <= 0;
end else if (adc_data_valid_i && adc_data_valid_q ) begin end else if (adc_data_valid_i && adc_data_valid_q ) begin
sample_counter <= sample_counter + 1; sample_counter <= sample_counter + 1;
@@ -143,8 +151,13 @@ lfsr_dither_enhanced #(
// Calculate phase increment for 120MHz IF at 400MHz sampling // Calculate phase increment for 120MHz IF at 400MHz sampling
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD; localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
// Apply dithering to reduce spurious tones // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
assign phase_inc_dithered = PHASE_INC_120MHZ + {24'b0, phase_dither_bits}; always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n)
phase_inc_dithered <= PHASE_INC_120MHZ;
else
phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
end
// ============================================================================ // ============================================================================
// Enhanced NCO with Diagnostics // Enhanced NCO with Diagnostics
@@ -161,11 +174,261 @@ nco_400m_enhanced nco_core (
); );
// ============================================================================ // ============================================================================
// Enhanced Mixing Stage with AGC // Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
//
// Architecture:
// ADC data → sign-extend to 18b → DSP48E1 A-port (AREG=1 pipelines it)
// NCO cos/sin → sign-extend to 18b → DSP48E1 B-port (BREG=1 pipelines it)
// Multiply result captured by MREG=1, then output registered by PREG=1
// force_saturation override applied AFTER DSP48E1 output (not on input path)
//
// Latency: 3 clock cycles (AREG/BREG + MREG + PREG)
// PREG=1 absorbs DSP48E1 CLK→P delay internally, preventing fabric timing violations
// In simulation (Icarus), uses behavioral equivalent since DSP48E1 is Xilinx-only
// ============================================================================
// Combinational ADC sign conversion (no register — DSP48E1 AREG handles it)
assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
// Valid pipeline: 3-stage shift register matching DSP48E1 AREG+MREG+PREG latency
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
dsp_valid_pipe <= 3'b000;
end else begin
dsp_valid_pipe <= {dsp_valid_pipe[1:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
end
end
`ifdef SIMULATION
// ---- Behavioral model for Icarus Verilog simulation ----
// Mimics DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 (3-cycle latency)
reg signed [MIXER_WIDTH-1:0] adc_signed_reg; // Models AREG
reg signed [15:0] cos_pipe_reg, sin_pipe_reg; // Models BREG
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Models MREG
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
// Stage 1: AREG/BREG equivalent
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
adc_signed_reg <= 0;
cos_pipe_reg <= 0;
sin_pipe_reg <= 0;
end else begin
adc_signed_reg <= adc_signed_w;
cos_pipe_reg <= cos_out;
sin_pipe_reg <= sin_out;
end
end
// Stage 2: MREG equivalent
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
mult_i_internal <= 0;
mult_q_internal <= 0;
end else begin
mult_i_internal <= $signed(adc_signed_reg) * $signed(cos_pipe_reg);
mult_q_internal <= $signed(adc_signed_reg) * $signed(sin_pipe_reg);
end
end
// Stage 3: PREG equivalent
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
mult_i_reg <= 0;
mult_q_reg <= 0;
end else begin
mult_i_reg <= mult_i_internal;
mult_q_reg <= mult_q_internal;
end
end
`else
// ---- Direct DSP48E1 instantiation for Vivado synthesis ----
// This guarantees AREG/BREG/MREG are used, achieving timing closure at 400 MHz
wire [47:0] dsp_p_i, dsp_p_q;
// DSP48E1 for I-channel mixer (adc_signed * cos_out)
DSP48E1 #(
// Feature control attributes
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
// Pipeline register attributes — all enabled for max timing
.AREG(1),
.BREG(1),
.MREG(1),
.PREG(1), // P register enabled — absorbs CLK→P delay for timing closure
.ADREG(0),
.ACASCREG(1),
.BCASCREG(1),
.ALUMODEREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.OPMODEREG(0),
// Pattern detector (unused)
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET")
) dsp_mixer_i (
// Clock and reset
.CLK(clk_400m),
.RSTA(!reset_n),
.RSTB(!reset_n),
.RSTM(!reset_n),
.RSTP(!reset_n),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
.RSTC(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
// Clock enables
.CEA1(1'b0), // AREG=1 uses CEA2
.CEA2(1'b1),
.CEB1(1'b0), // BREG=1 uses CEB2
.CEB2(1'b1),
.CEM(1'b1),
.CEP(1'b1), // P register clock enable (PREG=1)
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CEC(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
// Data ports
.A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}), // Sign-extend 18b to 30b
.B({{2{cos_out[15]}}, cos_out}), // Sign-extend 16b to 18b
.C(48'b0),
.D(25'b0),
.CARRYIN(1'b0),
// Control ports
.OPMODE(7'b0000101), // P = M (multiply only, no accumulate)
.ALUMODE(4'b0000), // Z + X + Y + CIN
.INMODE(5'b00000), // A2 * B2 (direct)
.CARRYINSEL(3'b000),
// Output ports
.P(dsp_p_i),
.PATTERNDETECT(),
.PATTERNBDETECT(),
.OVERFLOW(),
.UNDERFLOW(),
.CARRYOUT(),
// Cascade ports (unused)
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(1'b0),
.PCIN(48'b0),
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT()
);
// DSP48E1 for Q-channel mixer (adc_signed * sin_out)
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AREG(1),
.BREG(1),
.MREG(1),
.PREG(1),
.ADREG(0),
.ACASCREG(1),
.BCASCREG(1),
.ALUMODEREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.OPMODEREG(0),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET")
) dsp_mixer_q (
.CLK(clk_400m),
.RSTA(!reset_n),
.RSTB(!reset_n),
.RSTM(!reset_n),
.RSTP(!reset_n),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
.RSTC(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.CEA1(1'b0),
.CEA2(1'b1),
.CEB1(1'b0),
.CEB2(1'b1),
.CEM(1'b1),
.CEP(1'b1), // P register clock enable (PREG=1)
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CEC(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}),
.B({{2{sin_out[15]}}, sin_out}),
.C(48'b0),
.D(25'b0),
.CARRYIN(1'b0),
.OPMODE(7'b0000101),
.ALUMODE(4'b0000),
.INMODE(5'b00000),
.CARRYINSEL(3'b000),
.P(dsp_p_q),
.PATTERNDETECT(),
.PATTERNBDETECT(),
.OVERFLOW(),
.UNDERFLOW(),
.CARRYOUT(),
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(1'b0),
.PCIN(48'b0),
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT()
);
// Extract the multiply result from DSP48E1 P output
// adc_signed is 18 bits, NCO is 16 bits → product is 34 bits (bits [33:0] of P)
wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg = dsp_p_i[MIXER_WIDTH+NCO_WIDTH-1:0];
wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WIDTH-1:0];
`endif
// ============================================================================
// Post-DSP48E1 output stage: force_saturation override + overflow detection
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
// polluting the critical input path with extra logic
// ============================================================================ // ============================================================================
always @(posedge clk_400m or negedge reset_n) begin always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
adc_signed <= 0;
mixed_i <= 0; mixed_i <= 0;
mixed_q <= 0; mixed_q <= 0;
mixed_valid <= 0; mixed_valid <= 0;
@@ -173,29 +436,23 @@ always @(posedge clk_400m or negedge reset_n) begin
mixer_overflow_q <= 0; mixer_overflow_q <= 0;
saturation_count <= 0; saturation_count <= 0;
overflow_detected <= 0; overflow_detected <= 0;
end else if (nco_ready && adc_data_valid_i && adc_data_valid_q) begin end else if (dsp_valid_pipe[2]) begin
// Convert ADC data to signed with extended precision // Force saturation for testing (applied after DSP output, not on input path)
adc_signed <= {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
// Force saturation for testing
if (force_saturation_sync) begin if (force_saturation_sync) begin
mixed_i <= 34'h1FFFFFFFF; // Force positive saturation mixed_i <= 34'h1FFFFFFFF;
mixed_q <= 34'h200000000; // Force negative saturation mixed_q <= 34'h200000000;
mixer_overflow_i <= 1'b1; mixer_overflow_i <= 1'b1;
mixer_overflow_q <= 1'b1; mixer_overflow_q <= 1'b1;
end else begin end else begin
// Normal path: take DSP48E1 multiply result
mixed_i <= mult_i_reg;
mixed_q <= mult_q_reg;
// Normal mixing // Overflow detection on current cycle's multiply result
mixed_i <= $signed(adc_signed) * $signed(cos_out); mixer_overflow_i <= (mult_i_reg > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
mixed_q <= $signed(adc_signed) * $signed(sin_out); (mult_i_reg < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
mixer_overflow_q <= (mult_q_reg > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
(mult_q_reg < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
// Enhanced overflow detection with counting
mixer_overflow_i <= (mixed_i > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
(mixed_i < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
mixer_overflow_q <= (mixed_q > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
(mixed_q < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
end end
mixed_valid <= 1; mixed_valid <= 1;
9_Firmware/9_2_FPGA/nco_400m_enhanced.v
+245 -50
View File
@@ -11,11 +11,38 @@ module nco_400m_enhanced (
output reg dds_ready output reg dds_ready
); );
// Phase accumulator with registered outputs for better timing // ============================================================================
reg [31:0] phase_accumulator; // 4-stage pipelined NCO for 400 MHz timing closure
reg [31:0] phase_accumulator_reg; //
// Stage 1: Phase accumulator update (DSP48E1 in P=P+C mode) + offset addition
// DSP48E1 does: P_reg <= P_reg + C_port (frequency_tuning_word)
// The P register output IS the phase accumulator — no CARRY4 chain.
// phase_with_offset = P_output + {phase_offset, 16'b0} (registered)
// Stage 2: LUT address decode + LUT read → register abs values + quadrant
// Stage 3: Compute negations from registered abs values → register neg values
// (CARRY4 x4 chain has registered inputs, fits in 2.5ns easily)
// Stage 4: Quadrant sign application → sin_out, cos_out (pure MUX, no arith)
//
// Total latency: 4 cycles from phase_valid to sin/cos output
// Max logic levels per stage: Stage 1=DSP48E1(internal), Stage 2=2(LUT3+LUT6),
// Stage 3=4(CARRY4 chain), Stage 4=1(MUX)
// ============================================================================
// Phase accumulator — DSP48E1 P output provides the accumulated phase
// In simulation: behavioral reg. In synthesis: DSP48E1 P[31:0].
reg [31:0] phase_with_offset; reg [31:0] phase_with_offset;
reg phase_valid_delayed;
// Stage 2 pipeline registers: LUT output + quadrant
reg [15:0] sin_abs_reg, cos_abs_reg;
reg [1:0] quadrant_reg;
// Stage 3 pipeline registers: pre-computed negations + abs copies + quadrant
reg signed [15:0] sin_neg_reg, cos_neg_reg;
reg [15:0] sin_abs_reg2, cos_abs_reg2; // Pass-through for Stage 4 MUX
reg [1:0] quadrant_reg2; // Pass-through for Stage 4 MUX
// Valid pipeline: tracks 4-stage latency
reg [3:0] valid_pipe;
// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent) // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
wire [7:0] lut_address = phase_with_offset[31:24]; wire [7:0] lut_address = phase_with_offset[31:24];
@@ -51,61 +78,229 @@ initial begin
sin_lut[60] = 16'h7F61; sin_lut[61] = 16'h7FA6; sin_lut[62] = 16'h7FD8; sin_lut[63] = 16'h7FF5; sin_lut[60] = 16'h7F61; sin_lut[61] = 16'h7FA6; sin_lut[62] = 16'h7FD8; sin_lut[63] = 16'h7FF5;
end end
// Quadrant determination // Combinational: quadrant determination and LUT index (feeds Stage 2 registers)
wire [1:0] quadrant = lut_address[7:6]; // 00: Q1, 01: Q2, 10: Q3, 11: Q4 wire [1:0] quadrant_w = lut_address[7:6];
wire [5:0] lut_index = (quadrant[1] ? ~lut_address[5:0] : lut_address[5:0]); // Mirror for Q2/Q3 wire [5:0] lut_index = (quadrant_w[0] ^ quadrant_w[1]) ? ~lut_address[5:0] : lut_address[5:0];
// Sine and cosine calculation with quadrant mapping // Combinational LUT read (will be registered in Stage 2)
wire [15:0] sin_abs = sin_lut[lut_index]; wire [15:0] sin_abs_w = sin_lut[lut_index];
wire [15:0] cos_abs = sin_lut[63 - lut_index]; // Cosine is phase-shifted sine wire [15:0] cos_abs_w = sin_lut[63 - lut_index];
// ============================================================================
// Stage 1: Phase accumulator (DSP48E1) + offset addition (fabric register)
//
// The phase accumulator is the critical path bottleneck: a 32-bit addition
// requires 8 CARRY4 stages in fabric (2.826 ns > 2.5 ns budget at 400 MHz).
// Solution: Use DSP48E1 in P = P + C accumulate mode.
// - C-port carries frequency_tuning_word (zero-extended to 48 bits)
// - CREG=1 registers the tuning word inside the DSP
// - PREG=1 registers the accumulator output (P = P + C each cycle)
// - The DSP48E1 48-bit ALU performs the add internally at full speed
// - Only P[31:0] is used (32-bit phase accumulator)
//
// phase_with_offset is computed in fabric: DSP48E1 P output + {phase_offset, 16'b0}
// This is OK because both operands are registered (P is PREG output, phase_offset
// is a stable input), and the result feeds Stage 2 LUT which is also registered.
// ============================================================================
`ifdef SIMULATION
// ---- Behavioral model for Icarus Verilog simulation ----
// Mimics DSP48E1 accumulator: P <= P + C, with CREG=1, PREG=1
reg [31:0] phase_accumulator;
// Pipeline stage for better timing
always @(posedge clk_400m or negedge reset_n) begin always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
phase_accumulator <= 32'h00000000; phase_accumulator <= 32'h00000000;
phase_accumulator_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000; phase_with_offset <= 32'h00000000;
phase_valid_delayed <= 1'b0; end else if (phase_valid) begin
dds_ready <= 1'b0; phase_accumulator <= phase_accumulator + frequency_tuning_word;
phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
end
end
`else
// ---- DSP48E1 phase accumulator for Vivado synthesis ----
// P = P + C mode: accumulates frequency_tuning_word each clock cycle
// Uses 1 DSP48E1 (total design: 5 of 240 available = 2.08%)
wire [47:0] phase_accum_p; // DSP48E1 P output (48 bits, use [31:0])
DSP48E1 #(
// Feature control
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("NONE"), // No multiplier — pure ALU accumulate
.USE_SIMD("ONE48"),
// Pipeline registers
.AREG(0), // A-port unused for accumulate
.BREG(0), // B-port unused for accumulate
.CREG(1), // Register frequency_tuning_word on C-port
.MREG(0), // No multiplier
.PREG(1), // P register IS the phase accumulator
.ADREG(0),
.ACASCREG(0),
.BCASCREG(0),
.ALUMODEREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.DREG(0),
.INMODEREG(0),
.OPMODEREG(0),
// Pattern detector (unused)
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET")
) dsp_phase_accum (
// Clock and reset
.CLK(clk_400m),
.RSTA(1'b0),
.RSTB(1'b0),
.RSTM(1'b0),
.RSTP(!reset_n), // Reset P register (phase accumulator) on !reset_n
.RSTC(!reset_n), // Reset C register (tuning word) on !reset_n
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
// Clock enables
.CEA1(1'b0),
.CEA2(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b1), // Always register C (tuning word updates)
.CEM(1'b0),
.CEP(phase_valid), // Only accumulate when phase_valid is asserted
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
// Data ports
.A(30'b0), // Unused for P = P + C
.B(18'b0), // Unused for P = P + C
.C({16'b0, frequency_tuning_word}), // Zero-extend 32-bit FTW to 48 bits
.D(25'b0),
.CARRYIN(1'b0),
// Control ports
.OPMODE(7'b0010011), // Z=P (010), Y=0 (00), X=C_reg (11) → P = P + C
.ALUMODE(4'b0000), // Z + X + Y + CIN (standard add)
.INMODE(5'b00000),
.CARRYINSEL(3'b000),
// Output ports
.P(phase_accum_p),
.PATTERNDETECT(),
.PATTERNBDETECT(),
.OVERFLOW(),
.UNDERFLOW(),
.CARRYOUT(),
// Cascade ports (unused)
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(1'b0),
.PCIN(48'b0),
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT()
);
// phase_with_offset: add phase_offset to the DSP48E1 accumulator output
// Both operands are registered (phase_accum_p from PREG, phase_offset is stable input)
// This fabric add feeds Stage 2 LUT which is also registered — timing is fine
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
phase_with_offset <= 32'h00000000;
end else if (phase_valid) begin
phase_with_offset <= phase_accum_p[31:0] + {phase_offset, 16'b0};
end
end
`endif
// ============================================================================
// Stage 2: LUT read + register absolute values and quadrant
// Only LUT decode here — negation is deferred to Stage 3
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_abs_reg <= 16'h0000;
cos_abs_reg <= 16'h7FFF;
quadrant_reg <= 2'b00;
end else if (valid_pipe[0]) begin
sin_abs_reg <= sin_abs_w;
cos_abs_reg <= cos_abs_w;
quadrant_reg <= quadrant_w;
end
end
// ============================================================================
// Stage 3: Compute negations from registered abs values
// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
// Also pass through abs values and quadrant for Stage 4
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_neg_reg <= 16'h0000;
cos_neg_reg <= -16'h7FFF;
sin_abs_reg2 <= 16'h0000;
cos_abs_reg2 <= 16'h7FFF;
quadrant_reg2 <= 2'b00;
end else if (valid_pipe[1]) begin
sin_neg_reg <= -sin_abs_reg;
cos_neg_reg <= -cos_abs_reg;
sin_abs_reg2 <= sin_abs_reg;
cos_abs_reg2 <= cos_abs_reg;
quadrant_reg2 <= quadrant_reg;
end
end
// ============================================================================
// Stage 4: Quadrant sign application → final sin/cos output
// Uses pre-computed negated values from Stage 3 — pure MUX, no arithmetic
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_out <= 16'h0000; sin_out <= 16'h0000;
cos_out <= 16'h7FFF; cos_out <= 16'h7FFF;
end else if (valid_pipe[2]) begin
case (quadrant_reg2)
2'b00: begin // Quadrant I: sin+, cos+
sin_out <= sin_abs_reg2;
cos_out <= cos_abs_reg2;
end
2'b01: begin // Quadrant II: sin+, cos-
sin_out <= sin_abs_reg2;
cos_out <= cos_neg_reg;
end
2'b10: begin // Quadrant III: sin-, cos-
sin_out <= sin_neg_reg;
cos_out <= cos_neg_reg;
end
2'b11: begin // Quadrant IV: sin-, cos+
sin_out <= sin_neg_reg;
cos_out <= cos_abs_reg2;
end
endcase
end
end
// ============================================================================
// Valid pipeline and dds_ready (4-stage latency)
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
valid_pipe <= 4'b0000;
dds_ready <= 1'b0;
end else begin end else begin
phase_valid_delayed <= phase_valid; valid_pipe <= {valid_pipe[2:0], phase_valid};
dds_ready <= valid_pipe[3];
if (phase_valid) begin
// Update phase accumulator with dithered frequency tuning word
phase_accumulator <= phase_accumulator + frequency_tuning_word;
phase_accumulator_reg <= phase_accumulator;
// Apply phase offset
phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
dds_ready <= 1'b1;
end else begin
dds_ready <= 1'b0;
end
// Generate outputs with one cycle delay for pipelining
if (phase_valid_delayed) begin
// Calculate sine and cosine with proper quadrant signs
case (quadrant)
2'b00: begin // Quadrant I: sin+, cos+
sin_out <= sin_abs;
cos_out <= cos_abs;
end
2'b01: begin // Quadrant II: sin+, cos-
sin_out <= sin_abs;
cos_out <= -cos_abs;
end
2'b10: begin // Quadrant III: sin-, cos-
sin_out <= -sin_abs;
cos_out <= -cos_abs;
end
2'b11: begin // Quadrant IV: sin-, cos+
sin_out <= -sin_abs;
cos_out <= cos_abs;
end
endcase
end
end end
end end
9_Firmware/9_2_FPGA/radar_system_top.v
+2 -2
View File
@@ -191,7 +191,7 @@ BUFG bufg_ft601 (
); );
// Reset synchronization (clk_100m domain) // Reset synchronization (clk_100m domain)
reg [1:0] reset_sync; (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;
always @(posedge clk_100m_buf or negedge reset_n) begin always @(posedge clk_100m_buf or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
reset_sync <= 2'b00; reset_sync <= 2'b00;
@@ -204,7 +204,7 @@ assign sys_reset_n = reset_sync[1];
// Reset synchronization (clk_120m_dac domain) // Reset synchronization (clk_120m_dac domain)
// Ensures reset deassertion is synchronous to the DAC clock, // Ensures reset deassertion is synchronous to the DAC clock,
// preventing recovery/removal timing violations on 120 MHz FFs. // preventing recovery/removal timing violations on 120 MHz FFs.
reg [1:0] reset_sync_120m; (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_120m;
always @(posedge clk_120m_dac_buf or negedge reset_n) begin always @(posedge clk_120m_dac_buf or negedge reset_n) begin
if (!reset_n) begin if (!reset_n) begin
reset_sync_120m <= 2'b00; reset_sync_120m <= 2'b00;
9_Firmware/9_2_FPGA/tb/cic_dc_output.csv
+49 -49
View File
@@ -1,50 +1,50 @@
input_sample,output_sample,data_out,data_out_valid input_sample,output_sample,data_out,data_out_valid
5,0,0,1 6,0,0,1
9,1,0,1 10,1,0,1
13,2,0,1 14,2,0,1
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View File
@@ -5,11 +5,11 @@ sample,data_out
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9_Firmware/9_2_FPGA/tb/cic_sine_passband.csv
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View File
@@ -1,400 +1,400 @@
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1325,4619,330,4848 1326,4588,330,4914
1329,4490,331,4914 1330,4455,331,4960
1333,4343,332,4960 1334,4303,332,4988
1337,4179,333,4988 1338,4135,333,4995
1341,3998,334,4995 1342,3950,334,4983
1345,3802,335,4983 1346,3750,335,4951
1349,3590,336,4951 1350,3535,336,4899
1353,3365,337,4899 1354,3306,337,4828
1357,3126,338,4828 1358,3064,338,4738
1361,2875,339,4738 1362,2810,339,4630
1365,2612,340,4630 1366,2545,340,4503
1369,2339,341,4503 1370,2269,341,4358
1373,2057,342,4358 1374,1985,342,4196
1377,1767,343,4196 1378,1693,343,4018
1381,1470,344,4018 1382,1394,344,3824
1385,1167,345,3824 1386,1090,345,3614
1389,859,346,3614 1390,782,346,3390
1393,548,347,3390 1394,470,347,3154
1397,235,348,3154 1398,157,348,2904
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1405,-392,350,2643 1406,-470,350,2371
1409,-704,351,2371 1410,-782,351,2091
1413,-1013,352,2091 1414,-1090,352,1802
1417,-1319,353,1802 1418,-1394,353,1506
1421,-1619,354,1506 1422,-1693,354,1203
1425,-1913,355,1203 1426,-1985,355,896
1429,-2199,356,896 1430,-2269,356,586
1433,-2477,357,586 1434,-2545,357,274
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1445,-3247,360,-353 1446,-3306,360,-665
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399 1593 1594 -548 -470 397 -3391 -3155
400 1597 1598 -235 -157 398 -3155 -2905
9_Firmware/9_2_FPGA/tb/ddc_120mhz_output.csv
+3932 -3940
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File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/nco_120mhz_output.csv
+100 -100
View File
@@ -1,101 +1,101 @@
sample,sin_out,cos_out,dds_ready sample,sin_out,cos_out,dds_ready
0,0,32757,1 0,0,32767,0
1,9512,-31113,1 1,0,32767,0
2,-26319,-18868,1 2,0,32757,0
3,-18868,26319,1 3,31113,-9512,1
4,31113,9512,1 4,-26319,-18868,1
5,-32757,0,1 5,-26319,18868,1
6,-31113,9512,1 6,31113,9512,1
7,18868,26319,1 7,-32757,0,1
8,26319,-18868,1 8,-9512,31113,1
9,-9512,-31113,1 9,18868,26319,1
10,0,32757,1 10,18868,-26319,1
11,9512,-31113,1 11,-9512,-31113,1
12,-26319,-18868,1 12,0,32757,1
13,-18868,26319,1 13,31113,-9512,1
14,31113,9512,1 14,-26319,-18868,1
15,-32757,0,1 15,-26319,18868,1
16,-31113,9512,1 16,31113,9512,1
17,18868,26319,1 17,-32757,0,1
18,26319,-18868,1 18,-9512,31113,1
19,-9512,-31113,1 19,18868,26319,1
20,0,32757,1 20,18868,-26319,1
21,9512,-31113,1 21,-9512,-31113,1
22,-26319,-18868,1 22,0,32757,1
23,-18868,26319,1 23,31113,-9512,1
24,31113,9512,1 24,-26319,-18868,1
25,-32757,0,1 25,-26319,18868,1
26,-31113,9512,1 26,31113,9512,1
27,18868,26319,1 27,-32757,0,1
28,26319,-18868,1 28,-9512,31113,1
29,-9512,-31113,1 29,18868,26319,1
30,0,32757,1 30,18868,-26319,1
31,9512,-31113,1 31,-9512,-31113,1
32,-26319,-18868,1 32,0,32757,1
33,-18868,26319,1 33,31113,-9512,1
34,31113,9512,1 34,-26319,-18868,1
35,-32757,0,1 35,-26319,18868,1
36,-31113,9512,1 36,31113,9512,1
37,18868,26319,1 37,-32757,0,1
38,26319,-18868,1 38,-9512,31113,1
39,-9512,-31113,1 39,18868,26319,1
40,0,32757,1 40,18868,-26319,1
41,9512,-31113,1 41,-9512,-31113,1
42,-26319,-18868,1 42,0,32757,1
43,-18868,26319,1 43,31113,-9512,1
44,31113,9512,1 44,-26319,-18868,1
45,-32757,0,1 45,-26319,18868,1
46,-31113,9512,1 46,31113,9512,1
47,18868,26319,1 47,-32757,0,1
48,26319,-18868,1 48,-9512,31113,1
49,-9512,-31113,1 49,18868,26319,1
50,0,32757,1 50,18868,-26319,1
51,9512,-31113,1 51,-9512,-31113,1
52,-26319,-18868,1 52,0,32757,1
53,-18868,26319,1 53,31113,-9512,1
54,31113,9512,1 54,-26319,-18868,1
55,-32757,0,1 55,-26319,18868,1
56,-31113,9512,1 56,31113,9512,1
57,18868,26319,1 57,-32757,0,1
58,26319,-18868,1 58,-9512,31113,1
59,-9512,-31113,1 59,18868,26319,1
60,0,32757,1 60,18868,-26319,1
61,9512,-31113,1 61,-9512,-31113,1
62,-26319,-18868,1 62,0,32757,1
63,-18868,26319,1 63,31113,-9512,1
64,31113,9512,1 64,-26319,-18868,1
65,-32757,0,1 65,-26319,18868,1
66,-31113,9512,1 66,31113,9512,1
67,18868,26319,1 67,-32757,0,1
68,26319,-18868,1 68,-9512,31113,1
69,-9512,-31113,1 69,18868,26319,1
70,0,32757,1 70,18868,-26319,1
71,9512,-31113,1 71,-9512,-31113,1
72,-26319,-18868,1 72,0,32757,1
73,-18868,26319,1 73,31113,-9512,1
74,31113,9512,1 74,-26319,-18868,1
75,-32757,0,1 75,-26319,18868,1
76,-31113,9512,1 76,31113,9512,1
77,18868,26319,1 77,-32757,0,1
78,26319,-18868,1 78,-9512,31113,1
79,-9512,-31113,1 79,18868,26319,1
80,0,32757,1 80,18868,-26319,1
81,9512,-31113,1 81,-9512,-31113,1
82,-26319,-18868,1 82,0,32757,1
83,-18868,26319,1 83,31113,-9512,1
84,31113,9512,1 84,-26319,-18868,1
85,-32757,0,1 85,-26319,18868,1
86,-31113,9512,1 86,31113,9512,1
87,18868,26319,1 87,-32757,0,1
88,26319,-18868,1 88,-9512,31113,1
89,-9512,-31113,1 89,18868,26319,1
90,0,32757,1 90,18868,-26319,1
91,9512,-31113,1 91,-9512,-31113,1
92,-26319,-18868,1 92,0,32757,1
93,-18868,26319,1 93,31113,-9512,1
94,31113,9512,1 94,-26319,-18868,1
95,-32757,0,1 95,-26319,18868,1
96,-31113,9512,1 96,31113,9512,1
97,18868,26319,1 97,-32757,0,1
98,26319,-18868,1 98,-9512,31113,1
99,-9512,-31113,1 99,18868,26319,1
1 sample sin_out cos_out dds_ready
2 0 0 32757 32767 1 0
3 1 9512 0 -31113 32767 1 0
4 2 -26319 0 -18868 32757 1 0
5 3 -18868 31113 26319 -9512 1
6 4 31113 -26319 9512 -18868 1
7 5 -32757 -26319 0 18868 1
8 6 -31113 31113 9512 1
9 7 18868 -32757 26319 0 1
10 8 26319 -9512 -18868 31113 1
11 9 -9512 18868 -31113 26319 1
12 10 0 18868 32757 -26319 1
13 11 9512 -9512 -31113 1
14 12 -26319 0 -18868 32757 1
15 13 -18868 31113 26319 -9512 1
16 14 31113 -26319 9512 -18868 1
17 15 -32757 -26319 0 18868 1
18 16 -31113 31113 9512 1
19 17 18868 -32757 26319 0 1
20 18 26319 -9512 -18868 31113 1
21 19 -9512 18868 -31113 26319 1
22 20 0 18868 32757 -26319 1
23 21 9512 -9512 -31113 1
24 22 -26319 0 -18868 32757 1
25 23 -18868 31113 26319 -9512 1
26 24 31113 -26319 9512 -18868 1
27 25 -32757 -26319 0 18868 1
28 26 -31113 31113 9512 1
29 27 18868 -32757 26319 0 1
30 28 26319 -9512 -18868 31113 1
31 29 -9512 18868 -31113 26319 1
32 30 0 18868 32757 -26319 1
33 31 9512 -9512 -31113 1
34 32 -26319 0 -18868 32757 1
35 33 -18868 31113 26319 -9512 1
36 34 31113 -26319 9512 -18868 1
37 35 -32757 -26319 0 18868 1
38 36 -31113 31113 9512 1
39 37 18868 -32757 26319 0 1
40 38 26319 -9512 -18868 31113 1
41 39 -9512 18868 -31113 26319 1
42 40 0 18868 32757 -26319 1
43 41 9512 -9512 -31113 1
44 42 -26319 0 -18868 32757 1
45 43 -18868 31113 26319 -9512 1
46 44 31113 -26319 9512 -18868 1
47 45 -32757 -26319 0 18868 1
48 46 -31113 31113 9512 1
49 47 18868 -32757 26319 0 1
50 48 26319 -9512 -18868 31113 1
51 49 -9512 18868 -31113 26319 1
52 50 0 18868 32757 -26319 1
53 51 9512 -9512 -31113 1
54 52 -26319 0 -18868 32757 1
55 53 -18868 31113 26319 -9512 1
56 54 31113 -26319 9512 -18868 1
57 55 -32757 -26319 0 18868 1
58 56 -31113 31113 9512 1
59 57 18868 -32757 26319 0 1
60 58 26319 -9512 -18868 31113 1
61 59 -9512 18868 -31113 26319 1
62 60 0 18868 32757 -26319 1
63 61 9512 -9512 -31113 1
64 62 -26319 0 -18868 32757 1
65 63 -18868 31113 26319 -9512 1
66 64 31113 -26319 9512 -18868 1
67 65 -32757 -26319 0 18868 1
68 66 -31113 31113 9512 1
69 67 18868 -32757 26319 0 1
70 68 26319 -9512 -18868 31113 1
71 69 -9512 18868 -31113 26319 1
72 70 0 18868 32757 -26319 1
73 71 9512 -9512 -31113 1
74 72 -26319 0 -18868 32757 1
75 73 -18868 31113 26319 -9512 1
76 74 31113 -26319 9512 -18868 1
77 75 -32757 -26319 0 18868 1
78 76 -31113 31113 9512 1
79 77 18868 -32757 26319 0 1
80 78 26319 -9512 -18868 31113 1
81 79 -9512 18868 -31113 26319 1
82 80 0 18868 32757 -26319 1
83 81 9512 -9512 -31113 1
84 82 -26319 0 -18868 32757 1
85 83 -18868 31113 26319 -9512 1
86 84 31113 -26319 9512 -18868 1
87 85 -32757 -26319 0 18868 1
88 86 -31113 31113 9512 1
89 87 18868 -32757 26319 0 1
90 88 26319 -9512 -18868 31113 1
91 89 -9512 18868 -31113 26319 1
92 90 0 18868 32757 -26319 1
93 91 9512 -9512 -31113 1
94 92 -26319 0 -18868 32757 1
95 93 -18868 31113 26319 -9512 1
96 94 31113 -26319 9512 -18868 1
97 95 -32757 -26319 0 18868 1
98 96 -31113 31113 9512 1
99 97 18868 -32757 26319 0 1
100 98 26319 -9512 -18868 31113 1
101 99 -9512 18868 -31113 26319 1
9_Firmware/9_2_FPGA/tb/nco_1mhz_output.csv
+498 -498
View File
@@ -1,501 +1,501 @@
sample,sin_out,cos_out,dds_ready sample,sin_out,cos_out,dds_ready
0,0,32767,1 0,0,32767,0
1,0,32757,1 1,0,32767,0
2,0,32757,1 2,0,32767,0
3,804,32728,1 3,0,32757,0
4,804,32728,1 4,0,32757,1
5,1608,32678,1 5,804,32728,1
6,2410,32609,1 6,804,32728,1
7,2410,32609,1 7,1608,32678,1
8,3212,32521,1 8,2410,32609,1
9,4011,32412,1 9,2410,32609,1
10,4011,32412,1 10,3212,32521,1
11,4808,32285,1 11,4011,32412,1
12,5602,32137,1 12,4011,32412,1
13,5602,32137,1 13,4808,32285,1
14,6393,31971,1 14,5602,32137,1
15,6393,31971,1 15,5602,32137,1
16,7179,31785,1 16,6393,31971,1
17,7962,31580,1 17,6393,31971,1
18,7962,31580,1 18,7179,31785,1
19,8739,31356,1 19,7962,31580,1
20,9512,31113,1 20,7962,31580,1
21,9512,31113,1 21,8739,31356,1
22,10278,30852,1 22,9512,31113,1
23,11039,30571,1 23,9512,31113,1
24,11039,30571,1 24,10278,30852,1
25,11793,30273,1 25,11039,30571,1
26,11793,30273,1 26,11039,30571,1
27,12539,29956,1 27,11793,30273,1
28,13279,29621,1 28,11793,30273,1
29,13279,29621,1 29,12539,29956,1
30,14010,29268,1 30,13279,29621,1
31,14732,28898,1 31,13279,29621,1
32,14732,28898,1 32,14010,29268,1
33,15446,28510,1 33,14732,28898,1
34,16151,28105,1 34,14732,28898,1
35,16151,28105,1 35,15446,28510,1
36,16846,27683,1 36,16151,28105,1
37,17530,27245,1 37,16151,28105,1
38,17530,27245,1 38,16846,27683,1
39,18204,26790,1 39,17530,27245,1
40,18204,26790,1 40,17530,27245,1
41,18868,26319,1 41,18204,26790,1
42,19519,25832,1 42,18204,26790,1
43,19519,25832,1 43,18868,26319,1
44,20159,25329,1 44,19519,25832,1
45,20787,24811,1 45,19519,25832,1
46,20787,24811,1 46,20159,25329,1
47,21403,24279,1 47,20787,24811,1
48,22005,23731,1 48,20787,24811,1
49,22005,23731,1 49,21403,24279,1
50,22594,23170,1 50,22005,23731,1
51,22594,23170,1 51,22005,23731,1
52,23170,22594,1 52,22594,23170,1
53,23731,22005,1 53,22594,23170,1
54,23731,22005,1 54,23170,22594,1
55,24279,21403,1 55,23731,22005,1
56,24811,20787,1 56,23731,22005,1
57,24811,20787,1 57,24279,21403,1
58,25329,20159,1 58,24811,20787,1
59,25832,19519,1 59,24811,20787,1
60,25832,19519,1 60,25329,20159,1
61,26319,18868,1 61,25832,19519,1
62,26790,18204,1 62,25832,19519,1
63,26790,18204,1 63,26319,18868,1
64,27245,17530,1 64,26790,18204,1
65,27245,17530,1 65,26790,18204,1
66,27683,16846,1 66,27245,17530,1
67,28105,16151,1 67,27245,17530,1
68,28105,16151,1 68,27683,16846,1
69,28510,15446,1 69,28105,16151,1
70,28898,14732,1 70,28105,16151,1
71,28898,14732,1 71,28510,15446,1
72,29268,14010,1 72,28898,14732,1
73,29621,13279,1 73,28898,14732,1
74,29621,13279,1 74,29268,14010,1
75,29956,12539,1 75,29621,13279,1
76,29956,12539,1 76,29621,13279,1
77,30273,11793,1 77,29956,12539,1
78,30571,11039,1 78,29956,12539,1
79,30571,11039,1 79,30273,11793,1
80,30852,10278,1 80,30571,11039,1
81,31113,9512,1 81,30571,11039,1
82,31113,9512,1 82,30852,10278,1
83,31356,8739,1 83,31113,9512,1
84,31580,7962,1 84,31113,9512,1
85,31580,7962,1 85,31356,8739,1
86,31785,7179,1 86,31580,7962,1
87,31971,6393,1 87,31580,7962,1
88,31971,6393,1 88,31785,7179,1
89,32137,5602,1 89,31971,6393,1
90,32137,5602,1 90,31971,6393,1
91,32285,4808,1 91,32137,5602,1
92,32412,4011,1 92,32137,5602,1
93,32412,4011,1 93,32285,4808,1
94,32521,3212,1 94,32412,4011,1
95,32609,2410,1 95,32412,4011,1
96,32609,2410,1 96,32521,3212,1
97,32678,1608,1 97,32609,2410,1
98,32728,804,1 98,32609,2410,1
99,32728,804,1 99,32678,1608,1
100,32757,0,1 100,32728,804,1
101,32757,0,1 101,32728,804,1
102,0,-32757,1 102,32757,0,1
103,804,-32728,1 103,32757,0,1
104,804,-32728,1 104,32757,0,1
105,1608,-32678,1 105,32728,-804,1
106,2410,-32609,1 106,32728,-804,1
107,2410,-32609,1 107,32678,-1608,1
108,3212,-32521,1 108,32609,-2410,1
109,4011,-32412,1 109,32609,-2410,1
110,4011,-32412,1 110,32521,-3212,1
111,4808,-32285,1 111,32412,-4011,1
112,5602,-32137,1 112,32412,-4011,1
113,5602,-32137,1 113,32285,-4808,1
114,6393,-31971,1 114,32137,-5602,1
115,6393,-31971,1 115,32137,-5602,1
116,7179,-31785,1 116,31971,-6393,1
117,7962,-31580,1 117,31971,-6393,1
118,7962,-31580,1 118,31785,-7179,1
119,8739,-31356,1 119,31580,-7962,1
120,9512,-31113,1 120,31580,-7962,1
121,9512,-31113,1 121,31356,-8739,1
122,10278,-30852,1 122,31113,-9512,1
123,11039,-30571,1 123,31113,-9512,1
124,11039,-30571,1 124,30852,-10278,1
125,11793,-30273,1 125,30571,-11039,1
126,11793,-30273,1 126,30571,-11039,1
127,12539,-29956,1 127,30273,-11793,1
128,13279,-29621,1 128,30273,-11793,1
129,13279,-29621,1 129,29956,-12539,1
130,14010,-29268,1 130,29621,-13279,1
131,14732,-28898,1 131,29621,-13279,1
132,14732,-28898,1 132,29268,-14010,1
133,15446,-28510,1 133,28898,-14732,1
134,16151,-28105,1 134,28898,-14732,1
135,16151,-28105,1 135,28510,-15446,1
136,16846,-27683,1 136,28105,-16151,1
137,17530,-27245,1 137,28105,-16151,1
138,17530,-27245,1 138,27683,-16846,1
139,18204,-26790,1 139,27245,-17530,1
140,18204,-26790,1 140,27245,-17530,1
141,18868,-26319,1 141,26790,-18204,1
142,19519,-25832,1 142,26790,-18204,1
143,19519,-25832,1 143,26319,-18868,1
144,20159,-25329,1 144,25832,-19519,1
145,20787,-24811,1 145,25832,-19519,1
146,20787,-24811,1 146,25329,-20159,1
147,21403,-24279,1 147,24811,-20787,1
148,22005,-23731,1 148,24811,-20787,1
149,22005,-23731,1 149,24279,-21403,1
150,22594,-23170,1 150,23731,-22005,1
151,22594,-23170,1 151,23731,-22005,1
152,23170,-22594,1 152,23170,-22594,1
153,23731,-22005,1 153,23170,-22594,1
154,23731,-22005,1 154,22594,-23170,1
155,24279,-21403,1 155,22005,-23731,1
156,24811,-20787,1 156,22005,-23731,1
157,24811,-20787,1 157,21403,-24279,1
158,25329,-20159,1 158,20787,-24811,1
159,25832,-19519,1 159,20787,-24811,1
160,25832,-19519,1 160,20159,-25329,1
161,26319,-18868,1 161,19519,-25832,1
162,26790,-18204,1 162,19519,-25832,1
163,26790,-18204,1 163,18868,-26319,1
164,27245,-17530,1 164,18204,-26790,1
165,27245,-17530,1 165,18204,-26790,1
166,27683,-16846,1 166,17530,-27245,1
167,28105,-16151,1 167,17530,-27245,1
168,28105,-16151,1 168,16846,-27683,1
169,28510,-15446,1 169,16151,-28105,1
170,28898,-14732,1 170,16151,-28105,1
171,28898,-14732,1 171,15446,-28510,1
172,29268,-14010,1 172,14732,-28898,1
173,29621,-13279,1 173,14732,-28898,1
174,29621,-13279,1 174,14010,-29268,1
175,29956,-12539,1 175,13279,-29621,1
176,29956,-12539,1 176,13279,-29621,1
177,30273,-11793,1 177,12539,-29956,1
178,30571,-11039,1 178,12539,-29956,1
179,30571,-11039,1 179,11793,-30273,1
180,30852,-10278,1 180,11039,-30571,1
181,31113,-9512,1 181,11039,-30571,1
182,31113,-9512,1 182,10278,-30852,1
183,31356,-8739,1 183,9512,-31113,1
184,31580,-7962,1 184,9512,-31113,1
185,31580,-7962,1 185,8739,-31356,1
186,31785,-7179,1 186,7962,-31580,1
187,31971,-6393,1 187,7962,-31580,1
188,31971,-6393,1 188,7179,-31785,1
189,32137,-5602,1 189,6393,-31971,1
190,32137,-5602,1 190,6393,-31971,1
191,32285,-4808,1 191,5602,-32137,1
192,32412,-4011,1 192,5602,-32137,1
193,32412,-4011,1 193,4808,-32285,1
194,32521,-3212,1 194,4011,-32412,1
195,32609,-2410,1 195,4011,-32412,1
196,32609,-2410,1 196,3212,-32521,1
197,32678,-1608,1 197,2410,-32609,1
198,32728,-804,1 198,2410,-32609,1
199,32728,-804,1 199,1608,-32678,1
200,32757,0,1 200,804,-32728,1
201,32757,0,1 201,804,-32728,1
202,-32757,0,1 202,0,-32757,1
203,-32728,-804,1 203,0,-32757,1
204,-32728,-804,1 204,-32757,0,1
205,-32678,-1608,1 205,-32728,-804,1
206,-32609,-2410,1 206,-32728,-804,1
207,-32609,-2410,1 207,-32678,-1608,1
208,-32521,-3212,1 208,-32609,-2410,1
209,-32412,-4011,1 209,-32609,-2410,1
210,-32412,-4011,1 210,-32521,-3212,1
211,-32285,-4808,1 211,-32412,-4011,1
212,-32137,-5602,1 212,-32412,-4011,1
213,-32137,-5602,1 213,-32285,-4808,1
214,-31971,-6393,1 214,-32137,-5602,1
215,-31971,-6393,1 215,-32137,-5602,1
216,-31785,-7179,1 216,-31971,-6393,1
217,-31580,-7962,1 217,-31971,-6393,1
218,-31580,-7962,1 218,-31785,-7179,1
219,-31356,-8739,1 219,-31580,-7962,1
220,-31113,-9512,1 220,-31580,-7962,1
221,-31113,-9512,1 221,-31356,-8739,1
222,-30852,-10278,1 222,-31113,-9512,1
223,-30571,-11039,1 223,-31113,-9512,1
224,-30571,-11039,1 224,-30852,-10278,1
225,-30273,-11793,1 225,-30571,-11039,1
226,-30273,-11793,1 226,-30571,-11039,1
227,-29956,-12539,1 227,-30273,-11793,1
228,-29621,-13279,1 228,-30273,-11793,1
229,-29621,-13279,1 229,-29956,-12539,1
230,-29268,-14010,1 230,-29621,-13279,1
231,-28898,-14732,1 231,-29621,-13279,1
232,-28898,-14732,1 232,-29268,-14010,1
233,-28510,-15446,1 233,-28898,-14732,1
234,-28105,-16151,1 234,-28898,-14732,1
235,-28105,-16151,1 235,-28510,-15446,1
236,-27683,-16846,1 236,-28105,-16151,1
237,-27245,-17530,1 237,-28105,-16151,1
238,-27245,-17530,1 238,-27683,-16846,1
239,-26790,-18204,1 239,-27245,-17530,1
240,-26790,-18204,1 240,-27245,-17530,1
241,-26319,-18868,1 241,-26790,-18204,1
242,-25832,-19519,1 242,-26790,-18204,1
243,-25832,-19519,1 243,-26319,-18868,1
244,-25329,-20159,1 244,-25832,-19519,1
245,-24811,-20787,1 245,-25832,-19519,1
246,-24811,-20787,1 246,-25329,-20159,1
247,-24279,-21403,1 247,-24811,-20787,1
248,-23731,-22005,1 248,-24811,-20787,1
249,-23731,-22005,1 249,-24279,-21403,1
250,-23170,-22594,1 250,-23731,-22005,1
251,-23170,-22594,1 251,-23731,-22005,1
252,-22594,-23170,1 252,-23170,-22594,1
253,-22005,-23731,1 253,-23170,-22594,1
254,-22005,-23731,1 254,-22594,-23170,1
255,-21403,-24279,1 255,-22005,-23731,1
256,-20787,-24811,1 256,-22005,-23731,1
257,-20787,-24811,1 257,-21403,-24279,1
258,-20159,-25329,1 258,-20787,-24811,1
259,-19519,-25832,1 259,-20787,-24811,1
260,-19519,-25832,1 260,-20159,-25329,1
261,-18868,-26319,1 261,-19519,-25832,1
262,-18204,-26790,1 262,-19519,-25832,1
263,-18204,-26790,1 263,-18868,-26319,1
264,-17530,-27245,1 264,-18204,-26790,1
265,-17530,-27245,1 265,-18204,-26790,1
266,-16846,-27683,1 266,-17530,-27245,1
267,-16151,-28105,1 267,-17530,-27245,1
268,-16151,-28105,1 268,-16846,-27683,1
269,-15446,-28510,1 269,-16151,-28105,1
270,-14732,-28898,1 270,-16151,-28105,1
271,-14732,-28898,1 271,-15446,-28510,1
272,-14010,-29268,1 272,-14732,-28898,1
273,-13279,-29621,1 273,-14732,-28898,1
274,-13279,-29621,1 274,-14010,-29268,1
275,-12539,-29956,1 275,-13279,-29621,1
276,-12539,-29956,1 276,-13279,-29621,1
277,-11793,-30273,1 277,-12539,-29956,1
278,-11039,-30571,1 278,-12539,-29956,1
279,-11039,-30571,1 279,-11793,-30273,1
280,-10278,-30852,1 280,-11039,-30571,1
281,-9512,-31113,1 281,-11039,-30571,1
282,-9512,-31113,1 282,-10278,-30852,1
283,-8739,-31356,1 283,-9512,-31113,1
284,-7962,-31580,1 284,-9512,-31113,1
285,-7962,-31580,1 285,-8739,-31356,1
286,-7179,-31785,1 286,-7962,-31580,1
287,-6393,-31971,1 287,-7962,-31580,1
288,-6393,-31971,1 288,-7179,-31785,1
289,-5602,-32137,1 289,-6393,-31971,1
290,-5602,-32137,1 290,-6393,-31971,1
291,-4808,-32285,1 291,-5602,-32137,1
292,-4011,-32412,1 292,-5602,-32137,1
293,-4011,-32412,1 293,-4808,-32285,1
294,-3212,-32521,1 294,-4011,-32412,1
295,-2410,-32609,1 295,-4011,-32412,1
296,-2410,-32609,1 296,-3212,-32521,1
297,-1608,-32678,1 297,-2410,-32609,1
298,-804,-32728,1 298,-2410,-32609,1
299,-804,-32728,1 299,-1608,-32678,1
300,0,-32757,1 300,-804,-32728,1
301,0,-32757,1 301,-804,-32728,1
302,-32757,0,1 302,0,-32757,1
303,-32728,804,1 303,0,-32757,1
304,-32728,804,1 304,0,32757,1
305,-32678,1608,1 305,-804,32728,1
306,-32609,2410,1 306,-804,32728,1
307,-32609,2410,1 307,-1608,32678,1
308,-32521,3212,1 308,-2410,32609,1
309,-32412,4011,1 309,-2410,32609,1
310,-32412,4011,1 310,-3212,32521,1
311,-32285,4808,1 311,-4011,32412,1
312,-32137,5602,1 312,-4011,32412,1
313,-32137,5602,1 313,-4808,32285,1
314,-31971,6393,1 314,-5602,32137,1
315,-31971,6393,1 315,-5602,32137,1
316,-31785,7179,1 316,-6393,31971,1
317,-31580,7962,1 317,-6393,31971,1
318,-31580,7962,1 318,-7179,31785,1
319,-31356,8739,1 319,-7962,31580,1
320,-31113,9512,1 320,-7962,31580,1
321,-31113,9512,1 321,-8739,31356,1
322,-30852,10278,1 322,-9512,31113,1
323,-30571,11039,1 323,-9512,31113,1
324,-30571,11039,1 324,-10278,30852,1
325,-30273,11793,1 325,-11039,30571,1
326,-30273,11793,1 326,-11039,30571,1
327,-29956,12539,1 327,-11793,30273,1
328,-29621,13279,1 328,-11793,30273,1
329,-29621,13279,1 329,-12539,29956,1
330,-29268,14010,1 330,-13279,29621,1
331,-28898,14732,1 331,-13279,29621,1
332,-28898,14732,1 332,-14010,29268,1
333,-28510,15446,1 333,-14732,28898,1
334,-28105,16151,1 334,-14732,28898,1
335,-28105,16151,1 335,-15446,28510,1
336,-27683,16846,1 336,-16151,28105,1
337,-27245,17530,1 337,-16151,28105,1
338,-27245,17530,1 338,-16846,27683,1
339,-26790,18204,1 339,-17530,27245,1
340,-26790,18204,1 340,-17530,27245,1
341,-26319,18868,1 341,-18204,26790,1
342,-25832,19519,1 342,-18204,26790,1
343,-25832,19519,1 343,-18868,26319,1
344,-25329,20159,1 344,-19519,25832,1
345,-24811,20787,1 345,-19519,25832,1
346,-24811,20787,1 346,-20159,25329,1
347,-24279,21403,1 347,-20787,24811,1
348,-23731,22005,1 348,-20787,24811,1
349,-23731,22005,1 349,-21403,24279,1
350,-23170,22594,1 350,-22005,23731,1
351,-23170,22594,1 351,-22005,23731,1
352,-22594,23170,1 352,-22594,23170,1
353,-22005,23731,1 353,-22594,23170,1
354,-22005,23731,1 354,-23170,22594,1
355,-21403,24279,1 355,-23731,22005,1
356,-20787,24811,1 356,-23731,22005,1
357,-20787,24811,1 357,-24279,21403,1
358,-20159,25329,1 358,-24811,20787,1
359,-19519,25832,1 359,-24811,20787,1
360,-19519,25832,1 360,-25329,20159,1
361,-18868,26319,1 361,-25832,19519,1
362,-18204,26790,1 362,-25832,19519,1
363,-18204,26790,1 363,-26319,18868,1
364,-17530,27245,1 364,-26790,18204,1
365,-17530,27245,1 365,-26790,18204,1
366,-16846,27683,1 366,-27245,17530,1
367,-16151,28105,1 367,-27245,17530,1
368,-16151,28105,1 368,-27683,16846,1
369,-15446,28510,1 369,-28105,16151,1
370,-14732,28898,1 370,-28105,16151,1
371,-14732,28898,1 371,-28510,15446,1
372,-14010,29268,1 372,-28898,14732,1
373,-13279,29621,1 373,-28898,14732,1
374,-13279,29621,1 374,-29268,14010,1
375,-12539,29956,1 375,-29621,13279,1
376,-12539,29956,1 376,-29621,13279,1
377,-11793,30273,1 377,-29956,12539,1
378,-11039,30571,1 378,-29956,12539,1
379,-11039,30571,1 379,-30273,11793,1
380,-10278,30852,1 380,-30571,11039,1
381,-9512,31113,1 381,-30571,11039,1
382,-9512,31113,1 382,-30852,10278,1
383,-8739,31356,1 383,-31113,9512,1
384,-7962,31580,1 384,-31113,9512,1
385,-7962,31580,1 385,-31356,8739,1
386,-7179,31785,1 386,-31580,7962,1
387,-6393,31971,1 387,-31580,7962,1
388,-6393,31971,1 388,-31785,7179,1
389,-5602,32137,1 389,-31971,6393,1
390,-5602,32137,1 390,-31971,6393,1
391,-4808,32285,1 391,-32137,5602,1
392,-4011,32412,1 392,-32137,5602,1
393,-4011,32412,1 393,-32285,4808,1
394,-3212,32521,1 394,-32412,4011,1
395,-2410,32609,1 395,-32412,4011,1
396,-2410,32609,1 396,-32521,3212,1
397,-1608,32678,1 397,-32609,2410,1
398,-804,32728,1 398,-32609,2410,1
399,-804,32728,1 399,-32678,1608,1
400,0,32757,1 400,-32728,804,1
401,0,32757,1 401,-32728,804,1
402,0,32757,1 402,-32757,0,1
403,804,32728,1 403,-32757,0,1
404,804,32728,1 404,0,32757,1
405,1608,32678,1 405,804,32728,1
406,2410,32609,1 406,804,32728,1
407,2410,32609,1 407,1608,32678,1
408,3212,32521,1 408,2410,32609,1
409,4011,32412,1 409,2410,32609,1
410,4011,32412,1 410,3212,32521,1
411,4808,32285,1 411,4011,32412,1
412,5602,32137,1 412,4011,32412,1
413,5602,32137,1 413,4808,32285,1
414,6393,31971,1 414,5602,32137,1
415,6393,31971,1 415,5602,32137,1
416,7179,31785,1 416,6393,31971,1
417,7962,31580,1 417,6393,31971,1
418,7962,31580,1 418,7179,31785,1
419,8739,31356,1 419,7962,31580,1
420,9512,31113,1 420,7962,31580,1
421,9512,31113,1 421,8739,31356,1
422,10278,30852,1 422,9512,31113,1
423,11039,30571,1 423,9512,31113,1
424,11039,30571,1 424,10278,30852,1
425,11793,30273,1 425,11039,30571,1
426,11793,30273,1 426,11039,30571,1
427,12539,29956,1 427,11793,30273,1
428,13279,29621,1 428,11793,30273,1
429,13279,29621,1 429,12539,29956,1
430,14010,29268,1 430,13279,29621,1
431,14732,28898,1 431,13279,29621,1
432,14732,28898,1 432,14010,29268,1
433,15446,28510,1 433,14732,28898,1
434,16151,28105,1 434,14732,28898,1
435,16151,28105,1 435,15446,28510,1
436,16846,27683,1 436,16151,28105,1
437,17530,27245,1 437,16151,28105,1
438,17530,27245,1 438,16846,27683,1
439,18204,26790,1 439,17530,27245,1
440,18204,26790,1 440,17530,27245,1
441,18868,26319,1 441,18204,26790,1
442,19519,25832,1 442,18204,26790,1
443,19519,25832,1 443,18868,26319,1
444,20159,25329,1 444,19519,25832,1
445,20787,24811,1 445,19519,25832,1
446,20787,24811,1 446,20159,25329,1
447,21403,24279,1 447,20787,24811,1
448,22005,23731,1 448,20787,24811,1
449,22005,23731,1 449,21403,24279,1
450,22594,23170,1 450,22005,23731,1
451,22594,23170,1 451,22005,23731,1
452,23170,22594,1 452,22594,23170,1
453,23731,22005,1 453,22594,23170,1
454,23731,22005,1 454,23170,22594,1
455,24279,21403,1 455,23731,22005,1
456,24811,20787,1 456,23731,22005,1
457,24811,20787,1 457,24279,21403,1
458,25329,20159,1 458,24811,20787,1
459,25832,19519,1 459,24811,20787,1
460,25832,19519,1 460,25329,20159,1
461,26319,18868,1 461,25832,19519,1
462,26790,18204,1 462,25832,19519,1
463,26790,18204,1 463,26319,18868,1
464,27245,17530,1 464,26790,18204,1
465,27245,17530,1 465,26790,18204,1
466,27683,16846,1 466,27245,17530,1
467,28105,16151,1 467,27245,17530,1
468,28105,16151,1 468,27683,16846,1
469,28510,15446,1 469,28105,16151,1
470,28898,14732,1 470,28105,16151,1
471,28898,14732,1 471,28510,15446,1
472,29268,14010,1 472,28898,14732,1
473,29621,13279,1 473,28898,14732,1
474,29621,13279,1 474,29268,14010,1
475,29956,12539,1 475,29621,13279,1
476,29956,12539,1 476,29621,13279,1
477,30273,11793,1 477,29956,12539,1
478,30571,11039,1 478,29956,12539,1
479,30571,11039,1 479,30273,11793,1
480,30852,10278,1 480,30571,11039,1
481,31113,9512,1 481,30571,11039,1
482,31113,9512,1 482,30852,10278,1
483,31356,8739,1 483,31113,9512,1
484,31580,7962,1 484,31113,9512,1
485,31580,7962,1 485,31356,8739,1
486,31785,7179,1 486,31580,7962,1
487,31971,6393,1 487,31580,7962,1
488,31971,6393,1 488,31785,7179,1
489,32137,5602,1 489,31971,6393,1
490,32137,5602,1 490,31971,6393,1
491,32285,4808,1 491,32137,5602,1
492,32412,4011,1 492,32137,5602,1
493,32412,4011,1 493,32285,4808,1
494,32521,3212,1 494,32412,4011,1
495,32609,2410,1 495,32412,4011,1
496,32609,2410,1 496,32521,3212,1
497,32678,1608,1 497,32609,2410,1
498,32728,804,1 498,32609,2410,1
499,32728,804,1 499,32678,1608,1
1 sample sin_out cos_out dds_ready
2 0 0 32767 1 0
3 1 0 32757 32767 1 0
4 2 0 32757 32767 1 0
5 3 804 0 32728 32757 1 0
6 4 804 0 32728 32757 1
7 5 1608 804 32678 32728 1
8 6 2410 804 32609 32728 1
9 7 2410 1608 32609 32678 1
10 8 3212 2410 32521 32609 1
11 9 4011 2410 32412 32609 1
12 10 4011 3212 32412 32521 1
13 11 4808 4011 32285 32412 1
14 12 5602 4011 32137 32412 1
15 13 5602 4808 32137 32285 1
16 14 6393 5602 31971 32137 1
17 15 6393 5602 31971 32137 1
18 16 7179 6393 31785 31971 1
19 17 7962 6393 31580 31971 1
20 18 7962 7179 31580 31785 1
21 19 8739 7962 31356 31580 1
22 20 9512 7962 31113 31580 1
23 21 9512 8739 31113 31356 1
24 22 10278 9512 30852 31113 1
25 23 11039 9512 30571 31113 1
26 24 11039 10278 30571 30852 1
27 25 11793 11039 30273 30571 1
28 26 11793 11039 30273 30571 1
29 27 12539 11793 29956 30273 1
30 28 13279 11793 29621 30273 1
31 29 13279 12539 29621 29956 1
32 30 14010 13279 29268 29621 1
33 31 14732 13279 28898 29621 1
34 32 14732 14010 28898 29268 1
35 33 15446 14732 28510 28898 1
36 34 16151 14732 28105 28898 1
37 35 16151 15446 28105 28510 1
38 36 16846 16151 27683 28105 1
39 37 17530 16151 27245 28105 1
40 38 17530 16846 27245 27683 1
41 39 18204 17530 26790 27245 1
42 40 18204 17530 26790 27245 1
43 41 18868 18204 26319 26790 1
44 42 19519 18204 25832 26790 1
45 43 19519 18868 25832 26319 1
46 44 20159 19519 25329 25832 1
47 45 20787 19519 24811 25832 1
48 46 20787 20159 24811 25329 1
49 47 21403 20787 24279 24811 1
50 48 22005 20787 23731 24811 1
51 49 22005 21403 23731 24279 1
52 50 22594 22005 23170 23731 1
53 51 22594 22005 23170 23731 1
54 52 23170 22594 22594 23170 1
55 53 23731 22594 22005 23170 1
56 54 23731 23170 22005 22594 1
57 55 24279 23731 21403 22005 1
58 56 24811 23731 20787 22005 1
59 57 24811 24279 20787 21403 1
60 58 25329 24811 20159 20787 1
61 59 25832 24811 19519 20787 1
62 60 25832 25329 19519 20159 1
63 61 26319 25832 18868 19519 1
64 62 26790 25832 18204 19519 1
65 63 26790 26319 18204 18868 1
66 64 27245 26790 17530 18204 1
67 65 27245 26790 17530 18204 1
68 66 27683 27245 16846 17530 1
69 67 28105 27245 16151 17530 1
70 68 28105 27683 16151 16846 1
71 69 28510 28105 15446 16151 1
72 70 28898 28105 14732 16151 1
73 71 28898 28510 14732 15446 1
74 72 29268 28898 14010 14732 1
75 73 29621 28898 13279 14732 1
76 74 29621 29268 13279 14010 1
77 75 29956 29621 12539 13279 1
78 76 29956 29621 12539 13279 1
79 77 30273 29956 11793 12539 1
80 78 30571 29956 11039 12539 1
81 79 30571 30273 11039 11793 1
82 80 30852 30571 10278 11039 1
83 81 31113 30571 9512 11039 1
84 82 31113 30852 9512 10278 1
85 83 31356 31113 8739 9512 1
86 84 31580 31113 7962 9512 1
87 85 31580 31356 7962 8739 1
88 86 31785 31580 7179 7962 1
89 87 31971 31580 6393 7962 1
90 88 31971 31785 6393 7179 1
91 89 32137 31971 5602 6393 1
92 90 32137 31971 5602 6393 1
93 91 32285 32137 4808 5602 1
94 92 32412 32137 4011 5602 1
95 93 32412 32285 4011 4808 1
96 94 32521 32412 3212 4011 1
97 95 32609 32412 2410 4011 1
98 96 32609 32521 2410 3212 1
99 97 32678 32609 1608 2410 1
100 98 32728 32609 804 2410 1
101 99 32728 32678 804 1608 1
102 100 32757 32728 0 804 1
103 101 32757 32728 0 804 1
104 102 0 32757 -32757 0 1
105 103 804 32757 -32728 0 1
106 104 804 32757 -32728 0 1
107 105 1608 32728 -32678 -804 1
108 106 2410 32728 -32609 -804 1
109 107 2410 32678 -32609 -1608 1
110 108 3212 32609 -32521 -2410 1
111 109 4011 32609 -32412 -2410 1
112 110 4011 32521 -32412 -3212 1
113 111 4808 32412 -32285 -4011 1
114 112 5602 32412 -32137 -4011 1
115 113 5602 32285 -32137 -4808 1
116 114 6393 32137 -31971 -5602 1
117 115 6393 32137 -31971 -5602 1
118 116 7179 31971 -31785 -6393 1
119 117 7962 31971 -31580 -6393 1
120 118 7962 31785 -31580 -7179 1
121 119 8739 31580 -31356 -7962 1
122 120 9512 31580 -31113 -7962 1
123 121 9512 31356 -31113 -8739 1
124 122 10278 31113 -30852 -9512 1
125 123 11039 31113 -30571 -9512 1
126 124 11039 30852 -30571 -10278 1
127 125 11793 30571 -30273 -11039 1
128 126 11793 30571 -30273 -11039 1
129 127 12539 30273 -29956 -11793 1
130 128 13279 30273 -29621 -11793 1
131 129 13279 29956 -29621 -12539 1
132 130 14010 29621 -29268 -13279 1
133 131 14732 29621 -28898 -13279 1
134 132 14732 29268 -28898 -14010 1
135 133 15446 28898 -28510 -14732 1
136 134 16151 28898 -28105 -14732 1
137 135 16151 28510 -28105 -15446 1
138 136 16846 28105 -27683 -16151 1
139 137 17530 28105 -27245 -16151 1
140 138 17530 27683 -27245 -16846 1
141 139 18204 27245 -26790 -17530 1
142 140 18204 27245 -26790 -17530 1
143 141 18868 26790 -26319 -18204 1
144 142 19519 26790 -25832 -18204 1
145 143 19519 26319 -25832 -18868 1
146 144 20159 25832 -25329 -19519 1
147 145 20787 25832 -24811 -19519 1
148 146 20787 25329 -24811 -20159 1
149 147 21403 24811 -24279 -20787 1
150 148 22005 24811 -23731 -20787 1
151 149 22005 24279 -23731 -21403 1
152 150 22594 23731 -23170 -22005 1
153 151 22594 23731 -23170 -22005 1
154 152 23170 -22594 1
155 153 23731 23170 -22005 -22594 1
156 154 23731 22594 -22005 -23170 1
157 155 24279 22005 -21403 -23731 1
158 156 24811 22005 -20787 -23731 1
159 157 24811 21403 -20787 -24279 1
160 158 25329 20787 -20159 -24811 1
161 159 25832 20787 -19519 -24811 1
162 160 25832 20159 -19519 -25329 1
163 161 26319 19519 -18868 -25832 1
164 162 26790 19519 -18204 -25832 1
165 163 26790 18868 -18204 -26319 1
166 164 27245 18204 -17530 -26790 1
167 165 27245 18204 -17530 -26790 1
168 166 27683 17530 -16846 -27245 1
169 167 28105 17530 -16151 -27245 1
170 168 28105 16846 -16151 -27683 1
171 169 28510 16151 -15446 -28105 1
172 170 28898 16151 -14732 -28105 1
173 171 28898 15446 -14732 -28510 1
174 172 29268 14732 -14010 -28898 1
175 173 29621 14732 -13279 -28898 1
176 174 29621 14010 -13279 -29268 1
177 175 29956 13279 -12539 -29621 1
178 176 29956 13279 -12539 -29621 1
179 177 30273 12539 -11793 -29956 1
180 178 30571 12539 -11039 -29956 1
181 179 30571 11793 -11039 -30273 1
182 180 30852 11039 -10278 -30571 1
183 181 31113 11039 -9512 -30571 1
184 182 31113 10278 -9512 -30852 1
185 183 31356 9512 -8739 -31113 1
186 184 31580 9512 -7962 -31113 1
187 185 31580 8739 -7962 -31356 1
188 186 31785 7962 -7179 -31580 1
189 187 31971 7962 -6393 -31580 1
190 188 31971 7179 -6393 -31785 1
191 189 32137 6393 -5602 -31971 1
192 190 32137 6393 -5602 -31971 1
193 191 32285 5602 -4808 -32137 1
194 192 32412 5602 -4011 -32137 1
195 193 32412 4808 -4011 -32285 1
196 194 32521 4011 -3212 -32412 1
197 195 32609 4011 -2410 -32412 1
198 196 32609 3212 -2410 -32521 1
199 197 32678 2410 -1608 -32609 1
200 198 32728 2410 -804 -32609 1
201 199 32728 1608 -804 -32678 1
202 200 32757 804 0 -32728 1
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9_Firmware/9_2_FPGA/tb/nco_freq_switch.csv
+190 -190
View File
@@ -1,201 +1,201 @@
sample,sin_out,cos_out sample,sin_out,cos_out
0,22594,23170 0,22005,23731
1,26319,18868 1,22594,23170
2,28898,14732 2,22594,23170
3,31113,9512 3,26319,18868
4,32285,4808 4,28898,14732
5,32757,0 5,31113,9512
6,4808,-32285 6,32285,4808
7,9512,-31113 7,32757,0
8,14732,-28898 8,32285,-4808
9,18868,-26319 9,31113,-9512
10,22594,-23170 10,28898,-14732
11,26319,-18868 11,26319,-18868
12,28898,-14732 12,23170,-22594
13,31113,-9512 13,18868,-26319
14,32285,-4808 14,14732,-28898
15,32757,0 15,9512,-31113
16,-32285,-4808 16,4808,-32285
17,-31113,-9512 17,0,-32757
18,-28898,-14732 18,-32285,-4808
19,-26319,-18868 19,-31113,-9512
20,-23170,-22594 20,-28898,-14732
21,-18868,-26319 21,-26319,-18868
22,-14732,-28898 22,-23170,-22594
23,-9512,-31113 23,-18868,-26319
24,-4808,-32285 24,-14732,-28898
25,0,-32757 25,-9512,-31113
26,-32285,4808 26,-4808,-32285
27,-31113,9512 27,0,-32757
28,-28898,14732 28,-4808,32285
29,-26319,18868 29,-9512,31113
30,-23170,22594 30,-14732,28898
31,-18868,26319 31,-18868,26319
32,-14732,28898 32,-22594,23170
33,-9512,31113 33,-26319,18868
34,-4808,32285 34,-28898,14732
35,0,32757 35,-31113,9512
36,4808,32285 36,-32285,4808
37,9512,31113 37,-32757,0
38,14732,28898 38,4808,32285
39,18868,26319 39,9512,31113
40,22594,23170 40,14732,28898
41,26319,18868 41,18868,26319
42,28898,14732 42,22594,23170
43,31113,9512 43,26319,18868
44,32285,4808 44,28898,14732
45,32757,0 45,31113,9512
46,4808,-32285 46,32285,4808
47,9512,-31113 47,32757,0
48,14732,-28898 48,32285,-4808
49,18868,-26319 49,31113,-9512
50,22594,-23170 50,28898,-14732
51,26319,-18868 51,26319,-18868
52,28898,-14732 52,23170,-22594
53,31113,-9512 53,18868,-26319
54,32285,-4808 54,14732,-28898
55,32757,0 55,9512,-31113
56,-32285,-4808 56,4808,-32285
57,-31113,-9512 57,0,-32757
58,-28898,-14732 58,-32285,-4808
59,-26319,-18868 59,-31113,-9512
60,-23170,-22594 60,-28898,-14732
61,-18868,-26319 61,-26319,-18868
62,-14732,-28898 62,-23170,-22594
63,-9512,-31113 63,-18868,-26319
64,-4808,-32285 64,-14732,-28898
65,0,-32757 65,-9512,-31113
66,-32285,4808 66,-4808,-32285
67,-31113,9512 67,0,-32757
68,-28898,14732 68,-4808,32285
69,-26319,18868 69,-9512,31113
70,-23170,22594 70,-14732,28898
71,-18868,26319 71,-18868,26319
72,-14732,28898 72,-22594,23170
73,-9512,31113 73,-26319,18868
74,-4808,32285 74,-28898,14732
75,0,32757 75,-31113,9512
76,4808,32285 76,-32285,4808
77,9512,31113 77,-32757,0
78,14732,28898 78,4808,32285
79,18868,26319 79,9512,31113
80,22594,23170 80,14732,28898
81,26319,18868 81,18868,26319
82,28898,14732 82,22594,23170
83,31113,9512 83,26319,18868
84,32285,4808 84,28898,14732
85,32757,0 85,31113,9512
86,4808,-32285 86,32285,4808
87,9512,-31113 87,32757,0
88,14732,-28898 88,32285,-4808
89,18868,-26319 89,31113,-9512
90,22594,-23170 90,28898,-14732
91,26319,-18868 91,26319,-18868
92,28898,-14732 92,23170,-22594
93,31113,-9512 93,18868,-26319
94,32285,-4808 94,14732,-28898
95,32757,0 95,9512,-31113
96,-32285,-4808 96,4808,-32285
97,-31113,-9512 97,0,-32757
98,-28898,-14732 98,-32285,-4808
99,-26319,-18868 99,-31113,-9512
100,-23170,-22594 100,-28898,-14732
101,-18868,-26319 101,-26319,-18868
102,-14732,-28898 102,-23170,-22594
103,-9512,-31113 103,-18868,-26319
104,-4808,-32285 104,-14732,-28898
105,0,-32757 105,-9512,-31113
106,-32285,4808 106,-4808,-32285
107,-31113,9512 107,0,-32757
108,-28898,14732 108,-4808,32285
109,-26319,18868 109,-9512,31113
110,-23170,22594 110,-14732,28898
111,-18868,26319 111,-18868,26319
112,-14732,28898 112,-22594,23170
113,-9512,31113 113,-26319,18868
114,-4808,32285 114,-28898,14732
115,0,32757 115,-31113,9512
116,4808,32285 116,-32285,4808
117,9512,31113 117,-32757,0
118,14732,28898 118,4808,32285
119,18868,26319 119,9512,31113
120,22594,23170 120,14732,28898
121,26319,18868 121,18868,26319
122,28898,14732 122,22594,23170
123,31113,9512 123,26319,18868
124,32285,4808 124,28898,14732
125,32757,0 125,31113,9512
126,4808,-32285 126,32285,4808
127,9512,-31113 127,32757,0
128,14732,-28898 128,32285,-4808
129,18868,-26319 129,31113,-9512
130,22594,-23170 130,28898,-14732
131,26319,-18868 131,26319,-18868
132,28898,-14732 132,23170,-22594
133,31113,-9512 133,18868,-26319
134,32285,-4808 134,14732,-28898
135,32757,0 135,9512,-31113
136,-32285,-4808 136,4808,-32285
137,-31113,-9512 137,0,-32757
138,-28898,-14732 138,-32285,-4808
139,-26319,-18868 139,-31113,-9512
140,-23170,-22594 140,-28898,-14732
141,-18868,-26319 141,-26319,-18868
142,-14732,-28898 142,-23170,-22594
143,-9512,-31113 143,-18868,-26319
144,-4808,-32285 144,-14732,-28898
145,0,-32757 145,-9512,-31113
146,-32285,4808 146,-4808,-32285
147,-31113,9512 147,0,-32757
148,-28898,14732 148,-4808,32285
149,-26319,18868 149,-9512,31113
150,-23170,22594 150,-14732,28898
151,-18868,26319 151,-18868,26319
152,-14732,28898 152,-22594,23170
153,-9512,31113 153,-26319,18868
154,-4808,32285 154,-28898,14732
155,0,32757 155,-31113,9512
156,4808,32285 156,-32285,4808
157,9512,31113 157,-32757,0
158,14732,28898 158,4808,32285
159,18868,26319 159,9512,31113
160,22594,23170 160,14732,28898
161,26319,18868 161,18868,26319
162,28898,14732 162,22594,23170
163,31113,9512 163,26319,18868
164,32285,4808 164,28898,14732
165,32757,0 165,31113,9512
166,4808,-32285 166,32285,4808
167,9512,-31113 167,32757,0
168,14732,-28898 168,32285,-4808
169,18868,-26319 169,31113,-9512
170,22594,-23170 170,28898,-14732
171,26319,-18868 171,26319,-18868
172,28898,-14732 172,23170,-22594
173,31113,-9512 173,18868,-26319
174,32285,-4808 174,14732,-28898
175,32757,0 175,9512,-31113
176,-32285,-4808 176,4808,-32285
177,-31113,-9512 177,0,-32757
178,-28898,-14732 178,-32285,-4808
179,-26319,-18868 179,-31113,-9512
180,-23170,-22594 180,-28898,-14732
181,-18868,-26319 181,-26319,-18868
182,-14732,-28898 182,-23170,-22594
183,-9512,-31113 183,-18868,-26319
184,-4808,-32285 184,-14732,-28898
185,0,-32757 185,-9512,-31113
186,-32285,4808 186,-4808,-32285
187,-31113,9512 187,0,-32757
188,-28898,14732 188,-4808,32285
189,-26319,18868 189,-9512,31113
190,-23170,22594 190,-14732,28898
191,-18868,26319 191,-18868,26319
192,-14732,28898 192,-22594,23170
193,-9512,31113 193,-26319,18868
194,-4808,32285 194,-28898,14732
195,0,32757 195,-31113,9512
196,4808,32285 196,-32285,4808
197,9512,31113 197,-32757,0
198,14732,28898 198,4808,32285
199,18868,26319 199,9512,31113
1 sample sin_out cos_out
2 0 22594 22005 23170 23731
3 1 26319 22594 18868 23170
4 2 28898 22594 14732 23170
5 3 31113 26319 9512 18868
6 4 32285 28898 4808 14732
7 5 32757 31113 0 9512
8 6 4808 32285 -32285 4808
9 7 9512 32757 -31113 0
10 8 14732 32285 -28898 -4808
11 9 18868 31113 -26319 -9512
12 10 22594 28898 -23170 -14732
13 11 26319 -18868
14 12 28898 23170 -14732 -22594
15 13 31113 18868 -9512 -26319
16 14 32285 14732 -4808 -28898
17 15 32757 9512 0 -31113
18 16 -32285 4808 -4808 -32285
19 17 -31113 0 -9512 -32757
20 18 -28898 -32285 -14732 -4808
21 19 -26319 -31113 -18868 -9512
22 20 -23170 -28898 -22594 -14732
23 21 -18868 -26319 -26319 -18868
24 22 -14732 -23170 -28898 -22594
25 23 -9512 -18868 -31113 -26319
26 24 -4808 -14732 -32285 -28898
27 25 0 -9512 -32757 -31113
28 26 -32285 -4808 4808 -32285
29 27 -31113 0 9512 -32757
30 28 -28898 -4808 14732 32285
31 29 -26319 -9512 18868 31113
32 30 -23170 -14732 22594 28898
33 31 -18868 26319
34 32 -14732 -22594 28898 23170
35 33 -9512 -26319 31113 18868
36 34 -4808 -28898 32285 14732
37 35 0 -31113 32757 9512
38 36 4808 -32285 32285 4808
39 37 9512 -32757 31113 0
40 38 14732 4808 28898 32285
41 39 18868 9512 26319 31113
42 40 22594 14732 23170 28898
43 41 26319 18868 18868 26319
44 42 28898 22594 14732 23170
45 43 31113 26319 9512 18868
46 44 32285 28898 4808 14732
47 45 32757 31113 0 9512
48 46 4808 32285 -32285 4808
49 47 9512 32757 -31113 0
50 48 14732 32285 -28898 -4808
51 49 18868 31113 -26319 -9512
52 50 22594 28898 -23170 -14732
53 51 26319 -18868
54 52 28898 23170 -14732 -22594
55 53 31113 18868 -9512 -26319
56 54 32285 14732 -4808 -28898
57 55 32757 9512 0 -31113
58 56 -32285 4808 -4808 -32285
59 57 -31113 0 -9512 -32757
60 58 -28898 -32285 -14732 -4808
61 59 -26319 -31113 -18868 -9512
62 60 -23170 -28898 -22594 -14732
63 61 -18868 -26319 -26319 -18868
64 62 -14732 -23170 -28898 -22594
65 63 -9512 -18868 -31113 -26319
66 64 -4808 -14732 -32285 -28898
67 65 0 -9512 -32757 -31113
68 66 -32285 -4808 4808 -32285
69 67 -31113 0 9512 -32757
70 68 -28898 -4808 14732 32285
71 69 -26319 -9512 18868 31113
72 70 -23170 -14732 22594 28898
73 71 -18868 26319
74 72 -14732 -22594 28898 23170
75 73 -9512 -26319 31113 18868
76 74 -4808 -28898 32285 14732
77 75 0 -31113 32757 9512
78 76 4808 -32285 32285 4808
79 77 9512 -32757 31113 0
80 78 14732 4808 28898 32285
81 79 18868 9512 26319 31113
82 80 22594 14732 23170 28898
83 81 26319 18868 18868 26319
84 82 28898 22594 14732 23170
85 83 31113 26319 9512 18868
86 84 32285 28898 4808 14732
87 85 32757 31113 0 9512
88 86 4808 32285 -32285 4808
89 87 9512 32757 -31113 0
90 88 14732 32285 -28898 -4808
91 89 18868 31113 -26319 -9512
92 90 22594 28898 -23170 -14732
93 91 26319 -18868
94 92 28898 23170 -14732 -22594
95 93 31113 18868 -9512 -26319
96 94 32285 14732 -4808 -28898
97 95 32757 9512 0 -31113
98 96 -32285 4808 -4808 -32285
99 97 -31113 0 -9512 -32757
100 98 -28898 -32285 -14732 -4808
101 99 -26319 -31113 -18868 -9512
102 100 -23170 -28898 -22594 -14732
103 101 -18868 -26319 -26319 -18868
104 102 -14732 -23170 -28898 -22594
105 103 -9512 -18868 -31113 -26319
106 104 -4808 -14732 -32285 -28898
107 105 0 -9512 -32757 -31113
108 106 -32285 -4808 4808 -32285
109 107 -31113 0 9512 -32757
110 108 -28898 -4808 14732 32285
111 109 -26319 -9512 18868 31113
112 110 -23170 -14732 22594 28898
113 111 -18868 26319
114 112 -14732 -22594 28898 23170
115 113 -9512 -26319 31113 18868
116 114 -4808 -28898 32285 14732
117 115 0 -31113 32757 9512
118 116 4808 -32285 32285 4808
119 117 9512 -32757 31113 0
120 118 14732 4808 28898 32285
121 119 18868 9512 26319 31113
122 120 22594 14732 23170 28898
123 121 26319 18868 18868 26319
124 122 28898 22594 14732 23170
125 123 31113 26319 9512 18868
126 124 32285 28898 4808 14732
127 125 32757 31113 0 9512
128 126 4808 32285 -32285 4808
129 127 9512 32757 -31113 0
130 128 14732 32285 -28898 -4808
131 129 18868 31113 -26319 -9512
132 130 22594 28898 -23170 -14732
133 131 26319 -18868
134 132 28898 23170 -14732 -22594
135 133 31113 18868 -9512 -26319
136 134 32285 14732 -4808 -28898
137 135 32757 9512 0 -31113
138 136 -32285 4808 -4808 -32285
139 137 -31113 0 -9512 -32757
140 138 -28898 -32285 -14732 -4808
141 139 -26319 -31113 -18868 -9512
142 140 -23170 -28898 -22594 -14732
143 141 -18868 -26319 -26319 -18868
144 142 -14732 -23170 -28898 -22594
145 143 -9512 -18868 -31113 -26319
146 144 -4808 -14732 -32285 -28898
147 145 0 -9512 -32757 -31113
148 146 -32285 -4808 4808 -32285
149 147 -31113 0 9512 -32757
150 148 -28898 -4808 14732 32285
151 149 -26319 -9512 18868 31113
152 150 -23170 -14732 22594 28898
153 151 -18868 26319
154 152 -14732 -22594 28898 23170
155 153 -9512 -26319 31113 18868
156 154 -4808 -28898 32285 14732
157 155 0 -31113 32757 9512
158 156 4808 -32285 32285 4808
159 157 9512 -32757 31113 0
160 158 14732 4808 28898 32285
161 159 18868 9512 26319 31113
162 160 22594 14732 23170 28898
163 161 26319 18868 18868 26319
164 162 28898 22594 14732 23170
165 163 31113 26319 9512 18868
166 164 32285 28898 4808 14732
167 165 32757 31113 0 9512
168 166 4808 32285 -32285 4808
169 167 9512 32757 -31113 0
170 168 14732 32285 -28898 -4808
171 169 18868 31113 -26319 -9512
172 170 22594 28898 -23170 -14732
173 171 26319 -18868
174 172 28898 23170 -14732 -22594
175 173 31113 18868 -9512 -26319
176 174 32285 14732 -4808 -28898
177 175 32757 9512 0 -31113
178 176 -32285 4808 -4808 -32285
179 177 -31113 0 -9512 -32757
180 178 -28898 -32285 -14732 -4808
181 179 -26319 -31113 -18868 -9512
182 180 -23170 -28898 -22594 -14732
183 181 -18868 -26319 -26319 -18868
184 182 -14732 -23170 -28898 -22594
185 183 -9512 -18868 -31113 -26319
186 184 -4808 -14732 -32285 -28898
187 185 0 -9512 -32757 -31113
188 186 -32285 -4808 4808 -32285
189 187 -31113 0 9512 -32757
190 188 -28898 -4808 14732 32285
191 189 -26319 -9512 18868 31113
192 190 -23170 -14732 22594 28898
193 191 -18868 26319
194 192 -14732 -22594 28898 23170
195 193 -9512 -26319 31113 18868
196 194 -4808 -28898 32285 14732
197 195 0 -31113 32757 9512
198 196 4808 -32285 32285 4808
199 197 9512 -32757 31113 0
200 198 14732 4808 28898 32285
201 199 18868 9512 26319 31113
9_Firmware/9_2_FPGA/tb/nco_quadrature.csv
+20 -20
View File
@@ -7,16 +7,16 @@ sample,sin,cos,mag_sq
5,31113,9512,1058496913 5,31113,9512,1058496913
6,32285,4808,1065438089 6,32285,4808,1065438089
7,32757,0,1073021049 7,32757,0,1073021049
8,4808,-32285,1065438089 8,32285,-4808,1065438089
9,9512,-31113,1058496913 9,31113,-9512,1058496913
10,14732,-28898,1052126228 10,28898,-14732,1052126228
11,18868,-26319,1048691185 11,26319,-18868,1048691185
12,22594,-23170,1047337736 12,23170,-22594,1047337736
13,26319,-18868,1048691185 13,18868,-26319,1048691185
14,28898,-14732,1052126228 14,14732,-28898,1052126228
15,31113,-9512,1058496913 15,9512,-31113,1058496913
16,32285,-4808,1065438089 16,4808,-32285,1065438089
17,32757,0,1073021049 17,0,-32757,1073021049
18,-32285,-4808,1065438089 18,-32285,-4808,1065438089
19,-31113,-9512,1058496913 19,-31113,-9512,1058496913
20,-28898,-14732,1052126228 20,-28898,-14732,1052126228
@@ -27,15 +27,15 @@ sample,sin,cos,mag_sq
25,-9512,-31113,1058496913 25,-9512,-31113,1058496913
26,-4808,-32285,1065438089 26,-4808,-32285,1065438089
27,0,-32757,1073021049 27,0,-32757,1073021049
28,-32285,4808,1065438089 28,-4808,32285,1065438089
29,-31113,9512,1058496913 29,-9512,31113,1058496913
30,-28898,14732,1052126228 30,-14732,28898,1052126228
31,-26319,18868,1048691185 31,-18868,26319,1048691185
32,-23170,22594,1047337736 32,-22594,23170,1047337736
33,-18868,26319,1048691185 33,-26319,18868,1048691185
34,-14732,28898,1052126228 34,-28898,14732,1052126228
35,-9512,31113,1058496913 35,-31113,9512,1058496913
36,-4808,32285,1065438089 36,-32285,4808,1065438089
37,0,32757,1073021049 37,-32757,0,1073021049
38,4808,32285,1065438089 38,4808,32285,1065438089
39,9512,31113,1058496913 39,9512,31113,1058496913
1 sample sin cos mag_sq
7 5 31113 9512 1058496913
8 6 32285 4808 1065438089
9 7 32757 0 1073021049
10 8 4808 32285 -32285 -4808 1065438089
11 9 9512 31113 -31113 -9512 1058496913
12 10 14732 28898 -28898 -14732 1052126228
13 11 18868 26319 -26319 -18868 1048691185
14 12 22594 23170 -23170 -22594 1047337736
15 13 26319 18868 -18868 -26319 1048691185
16 14 28898 14732 -14732 -28898 1052126228
17 15 31113 9512 -9512 -31113 1058496913
18 16 32285 4808 -4808 -32285 1065438089
19 17 32757 0 0 -32757 1073021049
20 18 -32285 -4808 1065438089
21 19 -31113 -9512 1058496913
22 20 -28898 -14732 1052126228
27 25 -9512 -31113 1058496913
28 26 -4808 -32285 1065438089
29 27 0 -32757 1073021049
30 28 -32285 -4808 4808 32285 1065438089
31 29 -31113 -9512 9512 31113 1058496913
32 30 -28898 -14732 14732 28898 1052126228
33 31 -26319 -18868 18868 26319 1048691185
34 32 -23170 -22594 22594 23170 1047337736
35 33 -18868 -26319 26319 18868 1048691185
36 34 -14732 -28898 28898 14732 1052126228
37 35 -9512 -31113 31113 9512 1058496913
38 36 -4808 -32285 32285 4808 1065438089
39 37 0 -32757 32757 0 1073021049
40 38 4808 32285 1065438089
41 39 9512 31113 1058496913
9_Firmware/9_2_FPGA/tb/tb_nco_400m.v
+6 -6
View File
@@ -259,16 +259,16 @@ module tb_nco_400m;
#1; #1;
sin_before_gate = sin_out; sin_before_gate = sin_out;
// Deassert phase_valid // Deassert phase_valid — with 4-stage pipeline, dds_ready has 5-cycle latency
phase_valid = 0; phase_valid = 0;
@(posedge clk_400m); #1; repeat (6) @(posedge clk_400m); #1;
check(dds_ready === 1'b0, "dds_ready deasserts when phase_valid=0"); check(dds_ready === 1'b0, "dds_ready deasserts when phase_valid=0");
repeat (10) @(posedge clk_400m); repeat (10) @(posedge clk_400m);
// Re-enable // Re-enable — wait for pipeline to refill (5 cycles)
phase_valid = 1; phase_valid = 1;
@(posedge clk_400m); #1; repeat (6) @(posedge clk_400m); #1;
check(dds_ready === 1'b1, "dds_ready re-asserts when phase_valid=1"); check(dds_ready === 1'b1, "dds_ready re-asserts when phase_valid=1");
// ════════════════════════════════════════════════════════ // ════════════════════════════════════════════════════════
@@ -285,8 +285,8 @@ module tb_nco_400m;
frequency_tuning_word = FTW_10MHZ; frequency_tuning_word = FTW_10MHZ;
phase_valid = 1; phase_valid = 1;
// Skip pipeline warmup // Skip pipeline warmup (4-stage pipeline + 1 for dds_ready)
repeat (3) @(posedge clk_400m); repeat (5) @(posedge clk_400m);
mag_sq_min = 32'hFFFFFFFF; mag_sq_min = 32'hFFFFFFFF;
mag_sq_max = 32'h00000000; mag_sq_max = 32'h00000000;
9_Firmware/9_2_FPGA/usb_data_interface.v
+3 -3
View File
@@ -63,9 +63,9 @@ reg ft601_data_oe; // Output enable for bidirectional data bus
// Even though both are 100 MHz, they are asynchronous clocks and need synchronization. // Even though both are 100 MHz, they are asynchronous clocks and need synchronization.
// 2-stage synchronizers for valid signals // 2-stage synchronizers for valid signals
reg [1:0] range_valid_sync; (* ASYNC_REG = "TRUE" *) reg [1:0] range_valid_sync;
reg [1:0] doppler_valid_sync; (* ASYNC_REG = "TRUE" *) reg [1:0] doppler_valid_sync;
reg [1:0] cfar_valid_sync; (* ASYNC_REG = "TRUE" *) reg [1:0] cfar_valid_sync;
// Synchronized data captures (registered in ft601_clk_in domain) // Synchronized data captures (registered in ft601_clk_in domain)
reg [31:0] range_profile_cap; reg [31:0] range_profile_cap;