Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

Phase 0+ timing optimization (attempts #13-22 + implementation):

NCO (nco_400m_enhanced.v):
- 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX
- DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain)
- Registered phase_inc_dithered to break cascaded 32-bit add path

DDC (ddc_400m.v):
- Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1)
- CEP=1, RSTP=!reset_n for proper pipeline control
- 3-stage dsp_valid_pipe for PREG=1 latency
- Behavioral sim model under ifdef SIMULATION for Icarus compatibility

CIC (cic_decimator_4x_enhanced.v):
- 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28
- Removed integrator/comb saturation (CIC uses wrapping arithmetic by design)
- Pipelined output saturation comparison

CDC/ASYNC_REG:
- ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v,
  radar_system_top.v, usb_data_interface.v)
- Sync reset in generate blocks (cdc_modules.v)

Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints,
850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t.
All testbenches pass: 241/244 (3 known stub failures).
This commit is contained in:
Jason
2026-03-16 01:02:07 +02:00
parent 1e51b739a7
commit c983a3c705
15 changed files with 5883 additions and 5466 deletions
+20 -20
View File
@@ -7,16 +7,16 @@ sample,sin,cos,mag_sq
5,31113,9512,1058496913
6,32285,4808,1065438089
7,32757,0,1073021049
8,4808,-32285,1065438089
9,9512,-31113,1058496913
10,14732,-28898,1052126228
11,18868,-26319,1048691185
12,22594,-23170,1047337736
13,26319,-18868,1048691185
14,28898,-14732,1052126228
15,31113,-9512,1058496913
16,32285,-4808,1065438089
17,32757,0,1073021049
8,32285,-4808,1065438089
9,31113,-9512,1058496913
10,28898,-14732,1052126228
11,26319,-18868,1048691185
12,23170,-22594,1047337736
13,18868,-26319,1048691185
14,14732,-28898,1052126228
15,9512,-31113,1058496913
16,4808,-32285,1065438089
17,0,-32757,1073021049
18,-32285,-4808,1065438089
19,-31113,-9512,1058496913
20,-28898,-14732,1052126228
@@ -27,15 +27,15 @@ sample,sin,cos,mag_sq
25,-9512,-31113,1058496913
26,-4808,-32285,1065438089
27,0,-32757,1073021049
28,-32285,4808,1065438089
29,-31113,9512,1058496913
30,-28898,14732,1052126228
31,-26319,18868,1048691185
32,-23170,22594,1047337736
33,-18868,26319,1048691185
34,-14732,28898,1052126228
35,-9512,31113,1058496913
36,-4808,32285,1065438089
37,0,32757,1073021049
28,-4808,32285,1065438089
29,-9512,31113,1058496913
30,-14732,28898,1052126228
31,-18868,26319,1048691185
32,-22594,23170,1047337736
33,-26319,18868,1048691185
34,-28898,14732,1052126228
35,-31113,9512,1058496913
36,-32285,4808,1065438089
37,-32757,0,1073021049
38,4808,32285,1065438089
39,9512,31113,1058496913
1 sample sin cos mag_sq
7 5 31113 9512 1058496913
8 6 32285 4808 1065438089
9 7 32757 0 1073021049
10 8 4808 32285 -32285 -4808 1065438089
11 9 9512 31113 -31113 -9512 1058496913
12 10 14732 28898 -28898 -14732 1052126228
13 11 18868 26319 -26319 -18868 1048691185
14 12 22594 23170 -23170 -22594 1047337736
15 13 26319 18868 -18868 -26319 1048691185
16 14 28898 14732 -14732 -28898 1052126228
17 15 31113 9512 -9512 -31113 1058496913
18 16 32285 4808 -4808 -32285 1065438089
19 17 32757 0 0 -32757 1073021049
20 18 -32285 -4808 1065438089
21 19 -31113 -9512 1058496913
22 20 -28898 -14732 1052126228
27 25 -9512 -31113 1058496913
28 26 -4808 -32285 1065438089
29 27 0 -32757 1073021049
30 28 -32285 -4808 4808 32285 1065438089
31 29 -31113 -9512 9512 31113 1058496913
32 30 -28898 -14732 14732 28898 1052126228
33 31 -26319 -18868 18868 26319 1048691185
34 32 -23170 -22594 22594 23170 1047337736
35 33 -18868 -26319 26319 18868 1048691185
36 34 -14732 -28898 28898 14732 1052126228
37 35 -9512 -31113 31113 9512 1058496913
38 36 -4808 -32285 32285 4808 1065438089
39 37 0 -32757 32757 0 1073021049
40 38 4808 32285 1065438089
41 39 9512 31113 1058496913