Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

Phase 0+ timing optimization (attempts #13-22 + implementation):

NCO (nco_400m_enhanced.v):
- 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX
- DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain)
- Registered phase_inc_dithered to break cascaded 32-bit add path

DDC (ddc_400m.v):
- Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1)
- CEP=1, RSTP=!reset_n for proper pipeline control
- 3-stage dsp_valid_pipe for PREG=1 latency
- Behavioral sim model under ifdef SIMULATION for Icarus compatibility

CIC (cic_decimator_4x_enhanced.v):
- 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28
- Removed integrator/comb saturation (CIC uses wrapping arithmetic by design)
- Pipelined output saturation comparison

CDC/ASYNC_REG:
- ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v,
  radar_system_top.v, usb_data_interface.v)
- Sync reset in generate blocks (cdc_modules.v)

Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints,
850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t.
All testbenches pass: 241/244 (3 known stub failures).

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -191,7 +191,7 @@ BUFG bufg_ft601 (
 );
 
 // Reset synchronization (clk_100m domain)
-reg [1:0] reset_sync;
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;
 always @(posedge clk_100m_buf or negedge reset_n) begin
     if (!reset_n) begin
         reset_sync <= 2'b00;
@@ -204,7 +204,7 @@ assign sys_reset_n = reset_sync[1];
 // Reset synchronization (clk_120m_dac domain)
 // Ensures reset deassertion is synchronous to the DAC clock,
 // preventing recovery/removal timing violations on 120 MHz FFs.
-reg [1:0] reset_sync_120m;
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_120m;
 always @(posedge clk_120m_dac_buf or negedge reset_n) begin
     if (!reset_n) begin
         reset_sync_120m <= 2'b00;