Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).
This commit is contained in:
Jason
@@ -11,11 +11,38 @@ module nco_400m_enhanced (
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output reg dds_ready
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);
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// Phase accumulator with registered outputs for better timing
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reg [31:0] phase_accumulator;
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reg [31:0] phase_accumulator_reg;
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// ============================================================================
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// 4-stage pipelined NCO for 400 MHz timing closure
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//
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// Stage 1: Phase accumulator update (DSP48E1 in P=P+C mode) + offset addition
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// DSP48E1 does: P_reg <= P_reg + C_port (frequency_tuning_word)
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// The P register output IS the phase accumulator — no CARRY4 chain.
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// phase_with_offset = P_output + {phase_offset, 16'b0} (registered)
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// Stage 2: LUT address decode + LUT read → register abs values + quadrant
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// Stage 3: Compute negations from registered abs values → register neg values
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// (CARRY4 x4 chain has registered inputs, fits in 2.5ns easily)
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// Stage 4: Quadrant sign application → sin_out, cos_out (pure MUX, no arith)
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//
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// Total latency: 4 cycles from phase_valid to sin/cos output
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// Max logic levels per stage: Stage 1=DSP48E1(internal), Stage 2=2(LUT3+LUT6),
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// Stage 3=4(CARRY4 chain), Stage 4=1(MUX)
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// ============================================================================
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// Phase accumulator — DSP48E1 P output provides the accumulated phase
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// In simulation: behavioral reg. In synthesis: DSP48E1 P[31:0].
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reg [31:0] phase_with_offset;
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reg phase_valid_delayed;
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// Stage 2 pipeline registers: LUT output + quadrant
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reg [15:0] sin_abs_reg, cos_abs_reg;
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reg [1:0] quadrant_reg;
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// Stage 3 pipeline registers: pre-computed negations + abs copies + quadrant
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reg signed [15:0] sin_neg_reg, cos_neg_reg;
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reg [15:0] sin_abs_reg2, cos_abs_reg2; // Pass-through for Stage 4 MUX
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reg [1:0] quadrant_reg2; // Pass-through for Stage 4 MUX
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// Valid pipeline: tracks 4-stage latency
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reg [3:0] valid_pipe;
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// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
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wire [7:0] lut_address = phase_with_offset[31:24];
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@@ -51,61 +78,229 @@ initial begin
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sin_lut[60] = 16'h7F61; sin_lut[61] = 16'h7FA6; sin_lut[62] = 16'h7FD8; sin_lut[63] = 16'h7FF5;
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end
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// Quadrant determination
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wire [1:0] quadrant = lut_address[7:6]; // 00: Q1, 01: Q2, 10: Q3, 11: Q4
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wire [5:0] lut_index = (quadrant[1] ? ~lut_address[5:0] : lut_address[5:0]); // Mirror for Q2/Q3
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// Combinational: quadrant determination and LUT index (feeds Stage 2 registers)
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wire [1:0] quadrant_w = lut_address[7:6];
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wire [5:0] lut_index = (quadrant_w[0] ^ quadrant_w[1]) ? ~lut_address[5:0] : lut_address[5:0];
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// Sine and cosine calculation with quadrant mapping
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wire [15:0] sin_abs = sin_lut[lut_index];
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wire [15:0] cos_abs = sin_lut[63 - lut_index]; // Cosine is phase-shifted sine
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// Combinational LUT read (will be registered in Stage 2)
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wire [15:0] sin_abs_w = sin_lut[lut_index];
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wire [15:0] cos_abs_w = sin_lut[63 - lut_index];
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// ============================================================================
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// Stage 1: Phase accumulator (DSP48E1) + offset addition (fabric register)
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//
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// The phase accumulator is the critical path bottleneck: a 32-bit addition
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// requires 8 CARRY4 stages in fabric (2.826 ns > 2.5 ns budget at 400 MHz).
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// Solution: Use DSP48E1 in P = P + C accumulate mode.
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// - C-port carries frequency_tuning_word (zero-extended to 48 bits)
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// - CREG=1 registers the tuning word inside the DSP
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// - PREG=1 registers the accumulator output (P = P + C each cycle)
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// - The DSP48E1 48-bit ALU performs the add internally at full speed
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// - Only P[31:0] is used (32-bit phase accumulator)
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//
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// phase_with_offset is computed in fabric: DSP48E1 P output + {phase_offset, 16'b0}
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// This is OK because both operands are registered (P is PREG output, phase_offset
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// is a stable input), and the result feeds Stage 2 LUT which is also registered.
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// ============================================================================
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`ifdef SIMULATION
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// ---- Behavioral model for Icarus Verilog simulation ----
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// Mimics DSP48E1 accumulator: P <= P + C, with CREG=1, PREG=1
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reg [31:0] phase_accumulator;
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// Pipeline stage for better timing
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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phase_accumulator <= 32'h00000000;
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phase_accumulator_reg <= 32'h00000000;
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phase_with_offset <= 32'h00000000;
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phase_valid_delayed <= 1'b0;
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dds_ready <= 1'b0;
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end else if (phase_valid) begin
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phase_accumulator <= phase_accumulator + frequency_tuning_word;
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phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
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end
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end
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`else
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// ---- DSP48E1 phase accumulator for Vivado synthesis ----
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// P = P + C mode: accumulates frequency_tuning_word each clock cycle
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// Uses 1 DSP48E1 (total design: 5 of 240 available = 2.08%)
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wire [47:0] phase_accum_p; // DSP48E1 P output (48 bits, use [31:0])
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DSP48E1 #(
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// Feature control
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.A_INPUT("DIRECT"),
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.B_INPUT("DIRECT"),
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.USE_DPORT("FALSE"),
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.USE_MULT("NONE"), // No multiplier — pure ALU accumulate
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.USE_SIMD("ONE48"),
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// Pipeline registers
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.AREG(0), // A-port unused for accumulate
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.BREG(0), // B-port unused for accumulate
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.CREG(1), // Register frequency_tuning_word on C-port
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.MREG(0), // No multiplier
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.PREG(1), // P register IS the phase accumulator
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.ADREG(0),
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.ACASCREG(0),
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.BCASCREG(0),
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.ALUMODEREG(0),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.DREG(0),
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.INMODEREG(0),
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.OPMODEREG(0),
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// Pattern detector (unused)
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.AUTORESET_PATDET("NO_RESET"),
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.MASK(48'h3fffffffffff),
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.PATTERN(48'h000000000000),
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.SEL_MASK("MASK"),
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.SEL_PATTERN("PATTERN"),
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.USE_PATTERN_DETECT("NO_PATDET")
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) dsp_phase_accum (
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// Clock and reset
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.CLK(clk_400m),
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.RSTA(1'b0),
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.RSTB(1'b0),
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.RSTM(1'b0),
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.RSTP(!reset_n), // Reset P register (phase accumulator) on !reset_n
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.RSTC(!reset_n), // Reset C register (tuning word) on !reset_n
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.RSTALLCARRYIN(1'b0),
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.RSTALUMODE(1'b0),
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.RSTCTRL(1'b0),
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.RSTD(1'b0),
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.RSTINMODE(1'b0),
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// Clock enables
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.CEA1(1'b0),
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.CEA2(1'b0),
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.CEB1(1'b0),
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.CEB2(1'b0),
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.CEC(1'b1), // Always register C (tuning word updates)
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.CEM(1'b0),
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.CEP(phase_valid), // Only accumulate when phase_valid is asserted
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.CEAD(1'b0),
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.CEALUMODE(1'b0),
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.CECARRYIN(1'b0),
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.CECTRL(1'b0),
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.CED(1'b0),
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.CEINMODE(1'b0),
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// Data ports
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.A(30'b0), // Unused for P = P + C
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.B(18'b0), // Unused for P = P + C
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.C({16'b0, frequency_tuning_word}), // Zero-extend 32-bit FTW to 48 bits
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.D(25'b0),
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.CARRYIN(1'b0),
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// Control ports
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.OPMODE(7'b0010011), // Z=P (010), Y=0 (00), X=C_reg (11) → P = P + C
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.ALUMODE(4'b0000), // Z + X + Y + CIN (standard add)
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.INMODE(5'b00000),
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.CARRYINSEL(3'b000),
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// Output ports
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.P(phase_accum_p),
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.PATTERNDETECT(),
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.PATTERNBDETECT(),
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.OVERFLOW(),
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.UNDERFLOW(),
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.CARRYOUT(),
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// Cascade ports (unused)
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.ACIN(30'b0),
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.BCIN(18'b0),
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.CARRYCASCIN(1'b0),
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.MULTSIGNIN(1'b0),
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.PCIN(48'b0),
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.ACOUT(),
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.BCOUT(),
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.CARRYCASCOUT(),
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.MULTSIGNOUT(),
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.PCOUT()
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);
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// phase_with_offset: add phase_offset to the DSP48E1 accumulator output
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// Both operands are registered (phase_accum_p from PREG, phase_offset is stable input)
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// This fabric add feeds Stage 2 LUT which is also registered — timing is fine
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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phase_with_offset <= 32'h00000000;
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end else if (phase_valid) begin
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phase_with_offset <= phase_accum_p[31:0] + {phase_offset, 16'b0};
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end
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end
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`endif
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// ============================================================================
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// Stage 2: LUT read + register absolute values and quadrant
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// Only LUT decode here — negation is deferred to Stage 3
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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sin_abs_reg <= 16'h0000;
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cos_abs_reg <= 16'h7FFF;
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quadrant_reg <= 2'b00;
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end else if (valid_pipe[0]) begin
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sin_abs_reg <= sin_abs_w;
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cos_abs_reg <= cos_abs_w;
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quadrant_reg <= quadrant_w;
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end
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end
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// ============================================================================
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// Stage 3: Compute negations from registered abs values
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// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
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// Also pass through abs values and quadrant for Stage 4
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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sin_neg_reg <= 16'h0000;
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cos_neg_reg <= -16'h7FFF;
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sin_abs_reg2 <= 16'h0000;
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cos_abs_reg2 <= 16'h7FFF;
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quadrant_reg2 <= 2'b00;
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end else if (valid_pipe[1]) begin
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sin_neg_reg <= -sin_abs_reg;
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cos_neg_reg <= -cos_abs_reg;
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sin_abs_reg2 <= sin_abs_reg;
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cos_abs_reg2 <= cos_abs_reg;
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quadrant_reg2 <= quadrant_reg;
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end
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end
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// ============================================================================
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// Stage 4: Quadrant sign application → final sin/cos output
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// Uses pre-computed negated values from Stage 3 — pure MUX, no arithmetic
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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sin_out <= 16'h0000;
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cos_out <= 16'h7FFF;
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end else if (valid_pipe[2]) begin
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case (quadrant_reg2)
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2'b00: begin // Quadrant I: sin+, cos+
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sin_out <= sin_abs_reg2;
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cos_out <= cos_abs_reg2;
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end
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2'b01: begin // Quadrant II: sin+, cos-
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sin_out <= sin_abs_reg2;
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cos_out <= cos_neg_reg;
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end
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2'b10: begin // Quadrant III: sin-, cos-
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sin_out <= sin_neg_reg;
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cos_out <= cos_neg_reg;
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end
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2'b11: begin // Quadrant IV: sin-, cos+
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sin_out <= sin_neg_reg;
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cos_out <= cos_abs_reg2;
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end
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endcase
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end
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end
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// ============================================================================
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// Valid pipeline and dds_ready (4-stage latency)
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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valid_pipe <= 4'b0000;
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dds_ready <= 1'b0;
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end else begin
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phase_valid_delayed <= phase_valid;
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if (phase_valid) begin
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// Update phase accumulator with dithered frequency tuning word
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phase_accumulator <= phase_accumulator + frequency_tuning_word;
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phase_accumulator_reg <= phase_accumulator;
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// Apply phase offset
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phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
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dds_ready <= 1'b1;
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end else begin
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dds_ready <= 1'b0;
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end
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// Generate outputs with one cycle delay for pipelining
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if (phase_valid_delayed) begin
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// Calculate sine and cosine with proper quadrant signs
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case (quadrant)
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2'b00: begin // Quadrant I: sin+, cos+
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sin_out <= sin_abs;
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cos_out <= cos_abs;
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end
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2'b01: begin // Quadrant II: sin+, cos-
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sin_out <= sin_abs;
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cos_out <= -cos_abs;
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end
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2'b10: begin // Quadrant III: sin-, cos-
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sin_out <= -sin_abs;
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cos_out <= -cos_abs;
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end
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2'b11: begin // Quadrant IV: sin-, cos+
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sin_out <= -sin_abs;
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cos_out <= cos_abs;
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end
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endcase
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end
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valid_pipe <= {valid_pipe[2:0], phase_valid};
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dds_ready <= valid_pipe[3];
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end
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end
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