Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).
This commit is contained in:
Jason
@@ -2,6 +2,9 @@
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// ============================================================================
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// CDC FOR MULTI-BIT DATA (ADVANCED)
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// Uses Gray-code encoding with synchronous reset on sync chain to avoid
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// latch inference. ASYNC_REG attributes ensure Vivado places synchronizer
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// FFs in the same slice for optimal MTBF.
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// ============================================================================
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module cdc_adc_to_processing #(
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parameter WIDTH = 8,
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@@ -38,15 +41,16 @@ module cdc_adc_to_processing #(
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// Source domain registers
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reg [WIDTH-1:0] src_data_reg;
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reg [1:0] src_toggle = 2'b00;
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reg src_toggle_sync = 0;
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// Destination domain registers
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reg [WIDTH-1:0] dst_data_gray [0:STAGES-1];
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reg [1:0] dst_toggle_sync [0:STAGES-1];
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// Destination domain synchronizer registers
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// ASYNC_REG on memory arrays applies to all elements
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(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] dst_data_gray [0:STAGES-1];
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(* ASYNC_REG = "TRUE" *) reg [1:0] dst_toggle_sync [0:STAGES-1];
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reg [WIDTH-1:0] dst_data_reg;
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reg dst_valid_reg = 0;
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reg [1:0] prev_dst_toggle = 2'b00;
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// Source domain: capture data and toggle
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always @(posedge src_clk or negedge reset_n) begin
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if (!reset_n) begin
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src_data_reg <= 0;
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@@ -57,17 +61,16 @@ module cdc_adc_to_processing #(
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end
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end
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// CDC synchronization chain for data
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// CDC synchronization chain for data — SYNCHRONOUS RESET
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// Using synchronous reset avoids latch inference in Vivado.
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// For CDC synchronizers, synchronous reset is preferred because
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// the reset value is sampled safely within the clock domain.
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genvar i;
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generate
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for (i = 0; i < STAGES; i = i + 1) begin : data_sync_chain
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always @(posedge dst_clk or negedge reset_n) begin
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always @(posedge dst_clk) begin
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if (!reset_n) begin
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if (i == 0) begin
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dst_data_gray[i] <= 0;
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end else begin
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dst_data_gray[i] <= dst_data_gray[i-1];
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end
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dst_data_gray[i] <= 0;
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end else begin
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if (i == 0) begin
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// Convert to gray code at domain crossing
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@@ -80,13 +83,9 @@ module cdc_adc_to_processing #(
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end
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for (i = 0; i < STAGES; i = i + 1) begin : toggle_sync_chain
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always @(posedge dst_clk or negedge reset_n) begin
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always @(posedge dst_clk) begin
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if (!reset_n) begin
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if (i == 0) begin
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dst_toggle_sync[i] <= 2'b00;
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end else begin
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dst_toggle_sync[i] <= dst_toggle_sync[i-1];
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end
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dst_toggle_sync[i] <= 2'b00;
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end else begin
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if (i == 0) begin
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dst_toggle_sync[i] <= src_toggle;
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@@ -136,7 +135,7 @@ module cdc_single_bit #(
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output wire dst_signal
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);
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reg [STAGES-1:0] sync_chain;
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(* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] sync_chain;
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always @(posedge dst_clk or negedge reset_n) begin
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if (!reset_n) begin
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@@ -171,13 +170,13 @@ module cdc_handshake #(
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reg [WIDTH-1:0] src_data_reg;
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reg src_busy = 0;
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reg src_ack_sync = 0;
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reg [1:0] src_ack_sync_chain = 2'b00;
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(* ASYNC_REG = "TRUE" *) reg [1:0] src_ack_sync_chain = 2'b00;
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// Destination domain
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reg [WIDTH-1:0] dst_data_reg;
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reg dst_valid_reg = 0;
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reg dst_req_sync = 0;
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reg [1:0] dst_req_sync_chain = 2'b00;
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(* ASYNC_REG = "TRUE" *) reg [1:0] dst_req_sync_chain = 2'b00;
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reg dst_ack = 0;
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// Source clock domain
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@@ -234,4 +233,4 @@ module cdc_handshake #(
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assign dst_data = dst_data_reg;
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assign dst_valid = dst_valid_reg;
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endmodule
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endmodule
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@@ -15,20 +15,23 @@ parameter STAGES = 5;
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parameter DECIMATION = 4;
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parameter COMB_DELAY = 1;
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// Increased bit width for 18-bit input with headroom
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reg signed [35:0] integrator [0:STAGES-1]; // 36-bit for better dynamic range
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reg signed [35:0] comb [0:STAGES-1];
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reg signed [35:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
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// Enhanced control and monitoring
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reg [1:0] decimation_counter;
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reg data_valid_delayed;
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reg data_valid_comb;
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reg [7:0] output_counter;
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reg [35:0] max_integrator_value;
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reg overflow_detected;
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reg overflow_latched; // Latched overflow indicator
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// Accumulator width: input_width + N*log2(R) = 18 + 5*2 = 28 bits
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// (36-bit was over-provisioned; 28 bits is mathematically exact for R=4, N=5)
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localparam ACC_WIDTH = 28;
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reg signed [ACC_WIDTH-1:0] integrator [0:STAGES-1];
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reg signed [ACC_WIDTH-1:0] comb [0:STAGES-1];
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reg signed [ACC_WIDTH-1:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
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// Enhanced control and monitoring
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reg [1:0] decimation_counter;
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reg data_valid_delayed;
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reg data_valid_comb;
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reg [7:0] output_counter;
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reg [ACC_WIDTH-1:0] max_integrator_value;
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reg overflow_detected;
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reg overflow_latched; // Latched overflow indicator
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// Diagnostic registers
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reg [7:0] saturation_event_count;
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reg [31:0] sample_count;
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@@ -36,12 +39,18 @@ reg [31:0] sample_count;
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// Comb-stage saturation flags (separate from integrator block to avoid multi-driven nets)
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reg comb_overflow_latched;
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reg comb_saturation_detected;
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reg [7:0] comb_saturation_event_count;
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// Temporary signals for calculations
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reg signed [35:0] abs_integrator_value;
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reg signed [35:0] temp_scaled_output;
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reg [7:0] comb_saturation_event_count;
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// Temporary signals for calculations
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reg signed [ACC_WIDTH-1:0] abs_integrator_value;
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reg signed [ACC_WIDTH-1:0] temp_scaled_output;
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reg signed [17:0] temp_output; // Temporary output for proper range checking
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// Pipeline stage for saturation comparison — breaks CARRY4 chain from timing path
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reg sat_pos; // temp_scaled_output > 131071 (registered)
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reg sat_neg; // temp_scaled_output < -131072 (registered)
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reg signed [17:0] temp_output_pipe; // Registered passthrough value
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reg data_out_valid_pipe; // Delayed valid for pipelined output
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integer i, j;
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@@ -70,6 +79,10 @@ initial begin
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abs_integrator_value = 0;
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temp_scaled_output = 0;
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temp_output = 0;
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sat_pos = 0;
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sat_neg = 0;
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temp_output_pipe = 0;
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data_out_valid_pipe = 0;
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comb_overflow_latched = 0;
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comb_saturation_detected = 0;
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comb_saturation_event_count = 0;
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@@ -106,54 +119,23 @@ always @(posedge clk or negedge reset_n) begin
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if (data_valid) begin
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sample_count <= sample_count + 1;
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// First integrator stage with enhanced saturation detection
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if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) > (2**35 - 1)) begin
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integrator[0] <= (2**35 - 1);
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overflow_detected <= 1'b1;
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overflow_latched <= 1'b1;
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saturation_detected <= 1'b1;
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saturation_event_count <= saturation_event_count + 1;
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`ifdef SIMULATION
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$display("CIC_SATURATION: Positive overflow at sample %0d", sample_count);
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`endif
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end else if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) < -(2**35)) begin
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integrator[0] <= -(2**35);
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overflow_detected <= 1'b1;
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overflow_latched <= 1'b1;
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saturation_detected <= 1'b1;
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saturation_event_count <= saturation_event_count + 1;
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`ifdef SIMULATION
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$display("CIC_SATURATION: Negative overflow at sample %0d", sample_count);
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`endif
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end else begin
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integrator[0] <= integrator[0] + $signed({{18{data_in[17]}}, data_in});
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overflow_detected <= 1'b0; // Only clear immediate detection, not latched
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end
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// Integrator stages — standard CIC uses wrapping (modular) arithmetic.
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// Saturation clamping is removed because CIC math relies on wrap-around;
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// the comb stages difference successive integrator values, canceling wraps.
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integrator[0] <= integrator[0] + {{(ACC_WIDTH-18){data_in[17]}}, data_in};
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// Calculate absolute value for monitoring
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abs_integrator_value <= (integrator[0][35]) ? -integrator[0] : integrator[0];
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abs_integrator_value <= (integrator[0][ACC_WIDTH-1]) ? -integrator[0] : integrator[0];
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// Track maximum integrator value for gain monitoring (absolute value)
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if (abs_integrator_value > max_integrator_value) begin
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max_integrator_value <= abs_integrator_value;
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max_value_monitor <= abs_integrator_value[31:24];
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max_value_monitor <= abs_integrator_value[ACC_WIDTH-5:ACC_WIDTH-12];
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end
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// Remaining integrator stages with saturation protection
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// Remaining integrator stages — pure accumulation, no saturation
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for (i = 1; i < STAGES; i = i + 1) begin
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if (integrator[i] + integrator[i-1] > (2**35 - 1)) begin
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integrator[i] <= (2**35 - 1);
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overflow_detected <= 1'b1;
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overflow_latched <= 1'b1;
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saturation_detected <= 1'b1;
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end else if (integrator[i] + integrator[i-1] < -(2**35)) begin
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integrator[i] <= -(2**35);
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overflow_detected <= 1'b1;
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overflow_latched <= 1'b1;
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saturation_detected <= 1'b1;
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end else begin
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integrator[i] <= integrator[i] + integrator[i-1];
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end
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integrator[i] <= integrator[i] + integrator[i-1];
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end
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// Enhanced decimation control
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@@ -194,6 +176,10 @@ always @(posedge clk or negedge reset_n) begin
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data_out_valid <= 0;
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temp_scaled_output <= 0;
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temp_output <= 0;
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sat_pos <= 0;
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sat_neg <= 0;
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temp_output_pipe <= 0;
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data_out_valid_pipe <= 0;
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comb_overflow_latched <= 0;
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comb_saturation_detected <= 0;
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comb_saturation_event_count <= 0;
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@@ -207,21 +193,11 @@ always @(posedge clk or negedge reset_n) begin
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end
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if (data_valid_comb) begin
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// Enhanced comb processing with saturation check
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// Comb processing — raw subtraction only (no saturation check needed;
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// comb is a differencing stage, cannot overflow if integrators are bounded)
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for (i = 0; i < STAGES; i = i + 1) begin
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if (i == 0) begin
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// Check for comb stage saturation
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if (integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1] > (2**35 - 1)) begin
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comb[0] <= (2**35 - 1);
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comb_overflow_latched <= 1'b1;
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comb_saturation_detected <= 1'b1;
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end else if (integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1] < -(2**35)) begin
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comb[0] <= -(2**35);
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comb_overflow_latched <= 1'b1;
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comb_saturation_detected <= 1'b1;
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end else begin
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comb[0] <= integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1];
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end
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comb[0] <= integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1];
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// Update delay line for first stage
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for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
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@@ -229,18 +205,7 @@ always @(posedge clk or negedge reset_n) begin
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end
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comb_delay[0][0] <= integrator[STAGES-1];
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end else begin
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// Check for comb stage saturation
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if (comb[i-1] - comb_delay[i][COMB_DELAY-1] > (2**35 - 1)) begin
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comb[i] <= (2**35 - 1);
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comb_overflow_latched <= 1'b1;
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comb_saturation_detected <= 1'b1;
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end else if (comb[i-1] - comb_delay[i][COMB_DELAY-1] < -(2**35)) begin
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comb[i] <= -(2**35);
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comb_overflow_latched <= 1'b1;
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comb_saturation_detected <= 1'b1;
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end else begin
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comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
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end
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comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
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// Update delay line
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for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
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@@ -257,27 +222,36 @@ always @(posedge clk or negedge reset_n) begin
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// FIXED: Extract 18-bit output properly
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temp_output <= temp_scaled_output[17:0];
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// FIXED: Proper saturation detection for 18-bit signed range
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if (temp_scaled_output > 131071) begin // 2^17 - 1
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// Pipeline Stage 2: Register saturation comparison flags
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// This breaks the CARRY4 chain out of the data_out critical path
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sat_pos <= (temp_scaled_output > 131071);
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sat_neg <= (temp_scaled_output < -131072);
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temp_output_pipe <= temp_scaled_output[17:0];
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data_out_valid_pipe <= 1;
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end else begin
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data_out_valid_pipe <= 0;
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end
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// Pipeline Stage 3: MUX from registered comparison flags
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if (data_out_valid_pipe) begin
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if (sat_pos) begin
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data_out <= 131071;
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comb_overflow_latched <= 1'b1;
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comb_saturation_detected <= 1'b1;
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comb_saturation_event_count <= comb_saturation_event_count + 1;
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`ifdef SIMULATION
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$display("CIC_OUTPUT_SAT: TRUE Positive saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
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comb[STAGES-1], temp_scaled_output, temp_output, 131071);
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$display("CIC_OUTPUT_SAT: TRUE Positive saturation, final_out=%d", 131071);
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`endif
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end else if (temp_scaled_output < -131072) begin // -2^17
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end else if (sat_neg) begin
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data_out <= -131072;
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comb_overflow_latched <= 1'b1;
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comb_saturation_detected <= 1'b1;
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comb_saturation_event_count <= comb_saturation_event_count + 1;
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`ifdef SIMULATION
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$display("CIC_OUTPUT_SAT: TRUE Negative saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
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comb[STAGES-1], temp_scaled_output, temp_output, -131072);
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$display("CIC_OUTPUT_SAT: TRUE Negative saturation, final_out=%d", -131072);
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`endif
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end else begin
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data_out <= temp_output;
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data_out <= temp_output_pipe;
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comb_overflow_latched <= 1'b0;
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comb_saturation_detected <= 1'b0;
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end
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+349
-92
@@ -54,36 +54,41 @@ reg [2:0] saturation_count;
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reg overflow_detected;
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reg [7:0] error_counter;
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// CDC synchronization for control signals
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reg mixers_enable_sync;
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reg bypass_mode_sync;
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// Debug monitoring signals
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reg [31:0] sample_counter;
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wire signed [17:0] debug_mixed_i_trunc;
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wire signed [17:0] debug_mixed_q_trunc;
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// Real-time status monitoring
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// CDC synchronization for control signals (2-stage synchronizers)
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(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
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(* ASYNC_REG = "TRUE" *) reg [1:0] bypass_mode_sync_chain;
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(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
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wire mixers_enable_sync;
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wire bypass_mode_sync;
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wire force_saturation_sync;
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// Debug monitoring signals
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reg [31:0] sample_counter;
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wire signed [17:0] debug_mixed_i_trunc;
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wire signed [17:0] debug_mixed_q_trunc;
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// Real-time status monitoring
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reg [7:0] signal_power_i, signal_power_q;
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// Enhanced saturation injection for testing
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reg force_saturation_sync;
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// Internal mixing signals
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reg signed [MIXER_WIDTH-1:0] adc_signed;
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reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q;
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reg mixed_valid;
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reg mixer_overflow_i, mixer_overflow_q;
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// Internal mixing signals
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// DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 handles all internal pipelining
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// Latency: 3 cycles (1 for AREG/BREG, 1 for MREG, 1 for PREG)
|
||||
wire signed [MIXER_WIDTH-1:0] adc_signed_w;
|
||||
reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q;
|
||||
reg mixed_valid;
|
||||
reg mixer_overflow_i, mixer_overflow_q;
|
||||
// Pipeline valid tracking: 3-stage shift register to match DSP48E1 AREG+MREG+PREG latency
|
||||
reg [2:0] dsp_valid_pipe;
|
||||
|
||||
// Output stage registers
|
||||
reg signed [17:0] baseband_i_reg, baseband_q_reg;
|
||||
reg baseband_valid_reg;
|
||||
|
||||
// ============================================================================
|
||||
// Phase Dithering Signals
|
||||
// ============================================================================
|
||||
wire [7:0] phase_dither_bits;
|
||||
wire [31:0] phase_inc_dithered;
|
||||
// Phase Dithering Signals
|
||||
// ============================================================================
|
||||
wire [7:0] phase_dither_bits;
|
||||
reg [31:0] phase_inc_dithered;
|
||||
|
||||
|
||||
|
||||
@@ -97,27 +102,30 @@ assign debug_mixed_i_trunc = mixed_i[25:8];
|
||||
assign debug_mixed_q_trunc = mixed_q[25:8];
|
||||
|
||||
// ============================================================================
|
||||
// Clock Domain Crossing for Control Signals
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
mixers_enable_sync <= 1'b0;
|
||||
bypass_mode_sync <= 1'b0;
|
||||
force_saturation_sync <= 1'b0;
|
||||
end else begin
|
||||
mixers_enable_sync <= mixers_enable;
|
||||
bypass_mode_sync <= bypass_mode;
|
||||
force_saturation_sync <= force_saturation;
|
||||
end
|
||||
// Clock Domain Crossing for Control Signals (2-stage synchronizers)
|
||||
// ============================================================================
|
||||
assign mixers_enable_sync = mixers_enable_sync_chain[1];
|
||||
assign bypass_mode_sync = bypass_mode_sync_chain[1];
|
||||
assign force_saturation_sync = force_saturation_sync_chain[1];
|
||||
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
mixers_enable_sync_chain <= 2'b00;
|
||||
bypass_mode_sync_chain <= 2'b00;
|
||||
force_saturation_sync_chain <= 2'b00;
|
||||
end else begin
|
||||
mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
|
||||
bypass_mode_sync_chain <= {bypass_mode_sync_chain[0], bypass_mode};
|
||||
force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Sample Counter and Debug Monitoring
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n || reset_monitors) begin
|
||||
sample_counter <= 0;
|
||||
saturation_count <= 0;
|
||||
if (!reset_n || reset_monitors) begin
|
||||
sample_counter <= 0;
|
||||
error_counter <= 0;
|
||||
end else if (adc_data_valid_i && adc_data_valid_q ) begin
|
||||
sample_counter <= sample_counter + 1;
|
||||
@@ -143,8 +151,13 @@ lfsr_dither_enhanced #(
|
||||
// Calculate phase increment for 120MHz IF at 400MHz sampling
|
||||
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
|
||||
|
||||
// Apply dithering to reduce spurious tones
|
||||
assign phase_inc_dithered = PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
|
||||
// Apply dithering to reduce spurious tones (registered for 400 MHz timing)
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n)
|
||||
phase_inc_dithered <= PHASE_INC_120MHZ;
|
||||
else
|
||||
phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced NCO with Diagnostics
|
||||
@@ -160,59 +173,303 @@ nco_400m_enhanced nco_core (
|
||||
.dds_ready(nco_ready)
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Mixing Stage with AGC
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
adc_signed <= 0;
|
||||
mixed_i <= 0;
|
||||
mixed_q <= 0;
|
||||
mixed_valid <= 0;
|
||||
mixer_overflow_i <= 0;
|
||||
mixer_overflow_q <= 0;
|
||||
saturation_count <= 0;
|
||||
overflow_detected <= 0;
|
||||
end else if (nco_ready && adc_data_valid_i && adc_data_valid_q) begin
|
||||
// Convert ADC data to signed with extended precision
|
||||
adc_signed <= {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
|
||||
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
|
||||
|
||||
// Force saturation for testing
|
||||
if (force_saturation_sync) begin
|
||||
mixed_i <= 34'h1FFFFFFFF; // Force positive saturation
|
||||
mixed_q <= 34'h200000000; // Force negative saturation
|
||||
mixer_overflow_i <= 1'b1;
|
||||
mixer_overflow_q <= 1'b1;
|
||||
end else begin
|
||||
|
||||
// Normal mixing
|
||||
mixed_i <= $signed(adc_signed) * $signed(cos_out);
|
||||
mixed_q <= $signed(adc_signed) * $signed(sin_out);
|
||||
|
||||
|
||||
// Enhanced overflow detection with counting
|
||||
mixer_overflow_i <= (mixed_i > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
|
||||
(mixed_i < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
|
||||
mixer_overflow_q <= (mixed_q > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
|
||||
(mixed_q < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
|
||||
end
|
||||
|
||||
mixed_valid <= 1;
|
||||
|
||||
if (mixer_overflow_i || mixer_overflow_q) begin
|
||||
saturation_count <= saturation_count + 1;
|
||||
overflow_detected <= 1'b1;
|
||||
end else begin
|
||||
overflow_detected <= 1'b0;
|
||||
end
|
||||
|
||||
end else begin
|
||||
mixed_valid <= 0;
|
||||
mixer_overflow_i <= 0;
|
||||
mixer_overflow_q <= 0;
|
||||
overflow_detected <= 1'b0;
|
||||
end
|
||||
// ============================================================================
|
||||
// Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
|
||||
//
|
||||
// Architecture:
|
||||
// ADC data → sign-extend to 18b → DSP48E1 A-port (AREG=1 pipelines it)
|
||||
// NCO cos/sin → sign-extend to 18b → DSP48E1 B-port (BREG=1 pipelines it)
|
||||
// Multiply result captured by MREG=1, then output registered by PREG=1
|
||||
// force_saturation override applied AFTER DSP48E1 output (not on input path)
|
||||
//
|
||||
// Latency: 3 clock cycles (AREG/BREG + MREG + PREG)
|
||||
// PREG=1 absorbs DSP48E1 CLK→P delay internally, preventing fabric timing violations
|
||||
// In simulation (Icarus), uses behavioral equivalent since DSP48E1 is Xilinx-only
|
||||
// ============================================================================
|
||||
|
||||
// Combinational ADC sign conversion (no register — DSP48E1 AREG handles it)
|
||||
assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
|
||||
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
|
||||
|
||||
// Valid pipeline: 3-stage shift register matching DSP48E1 AREG+MREG+PREG latency
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
dsp_valid_pipe <= 3'b000;
|
||||
end else begin
|
||||
dsp_valid_pipe <= {dsp_valid_pipe[1:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
|
||||
end
|
||||
end
|
||||
|
||||
`ifdef SIMULATION
|
||||
// ---- Behavioral model for Icarus Verilog simulation ----
|
||||
// Mimics DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 (3-cycle latency)
|
||||
reg signed [MIXER_WIDTH-1:0] adc_signed_reg; // Models AREG
|
||||
reg signed [15:0] cos_pipe_reg, sin_pipe_reg; // Models BREG
|
||||
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Models MREG
|
||||
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
|
||||
|
||||
// Stage 1: AREG/BREG equivalent
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
adc_signed_reg <= 0;
|
||||
cos_pipe_reg <= 0;
|
||||
sin_pipe_reg <= 0;
|
||||
end else begin
|
||||
adc_signed_reg <= adc_signed_w;
|
||||
cos_pipe_reg <= cos_out;
|
||||
sin_pipe_reg <= sin_out;
|
||||
end
|
||||
end
|
||||
|
||||
// Stage 2: MREG equivalent
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
mult_i_internal <= 0;
|
||||
mult_q_internal <= 0;
|
||||
end else begin
|
||||
mult_i_internal <= $signed(adc_signed_reg) * $signed(cos_pipe_reg);
|
||||
mult_q_internal <= $signed(adc_signed_reg) * $signed(sin_pipe_reg);
|
||||
end
|
||||
end
|
||||
|
||||
// Stage 3: PREG equivalent
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
mult_i_reg <= 0;
|
||||
mult_q_reg <= 0;
|
||||
end else begin
|
||||
mult_i_reg <= mult_i_internal;
|
||||
mult_q_reg <= mult_q_internal;
|
||||
end
|
||||
end
|
||||
|
||||
`else
|
||||
// ---- Direct DSP48E1 instantiation for Vivado synthesis ----
|
||||
// This guarantees AREG/BREG/MREG are used, achieving timing closure at 400 MHz
|
||||
wire [47:0] dsp_p_i, dsp_p_q;
|
||||
|
||||
// DSP48E1 for I-channel mixer (adc_signed * cos_out)
|
||||
DSP48E1 #(
|
||||
// Feature control attributes
|
||||
.A_INPUT("DIRECT"),
|
||||
.B_INPUT("DIRECT"),
|
||||
.USE_DPORT("FALSE"),
|
||||
.USE_MULT("MULTIPLY"),
|
||||
.USE_SIMD("ONE48"),
|
||||
// Pipeline register attributes — all enabled for max timing
|
||||
.AREG(1),
|
||||
.BREG(1),
|
||||
.MREG(1),
|
||||
.PREG(1), // P register enabled — absorbs CLK→P delay for timing closure
|
||||
.ADREG(0),
|
||||
.ACASCREG(1),
|
||||
.BCASCREG(1),
|
||||
.ALUMODEREG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSELREG(0),
|
||||
.CREG(0),
|
||||
.DREG(0),
|
||||
.INMODEREG(0),
|
||||
.OPMODEREG(0),
|
||||
// Pattern detector (unused)
|
||||
.AUTORESET_PATDET("NO_RESET"),
|
||||
.MASK(48'h3fffffffffff),
|
||||
.PATTERN(48'h000000000000),
|
||||
.SEL_MASK("MASK"),
|
||||
.SEL_PATTERN("PATTERN"),
|
||||
.USE_PATTERN_DETECT("NO_PATDET")
|
||||
) dsp_mixer_i (
|
||||
// Clock and reset
|
||||
.CLK(clk_400m),
|
||||
.RSTA(!reset_n),
|
||||
.RSTB(!reset_n),
|
||||
.RSTM(!reset_n),
|
||||
.RSTP(!reset_n),
|
||||
.RSTALLCARRYIN(1'b0),
|
||||
.RSTALUMODE(1'b0),
|
||||
.RSTCTRL(1'b0),
|
||||
.RSTC(1'b0),
|
||||
.RSTD(1'b0),
|
||||
.RSTINMODE(1'b0),
|
||||
// Clock enables
|
||||
.CEA1(1'b0), // AREG=1 uses CEA2
|
||||
.CEA2(1'b1),
|
||||
.CEB1(1'b0), // BREG=1 uses CEB2
|
||||
.CEB2(1'b1),
|
||||
.CEM(1'b1),
|
||||
.CEP(1'b1), // P register clock enable (PREG=1)
|
||||
.CEAD(1'b0),
|
||||
.CEALUMODE(1'b0),
|
||||
.CECARRYIN(1'b0),
|
||||
.CECTRL(1'b0),
|
||||
.CEC(1'b0),
|
||||
.CED(1'b0),
|
||||
.CEINMODE(1'b0),
|
||||
// Data ports
|
||||
.A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}), // Sign-extend 18b to 30b
|
||||
.B({{2{cos_out[15]}}, cos_out}), // Sign-extend 16b to 18b
|
||||
.C(48'b0),
|
||||
.D(25'b0),
|
||||
.CARRYIN(1'b0),
|
||||
// Control ports
|
||||
.OPMODE(7'b0000101), // P = M (multiply only, no accumulate)
|
||||
.ALUMODE(4'b0000), // Z + X + Y + CIN
|
||||
.INMODE(5'b00000), // A2 * B2 (direct)
|
||||
.CARRYINSEL(3'b000),
|
||||
// Output ports
|
||||
.P(dsp_p_i),
|
||||
.PATTERNDETECT(),
|
||||
.PATTERNBDETECT(),
|
||||
.OVERFLOW(),
|
||||
.UNDERFLOW(),
|
||||
.CARRYOUT(),
|
||||
// Cascade ports (unused)
|
||||
.ACIN(30'b0),
|
||||
.BCIN(18'b0),
|
||||
.CARRYCASCIN(1'b0),
|
||||
.MULTSIGNIN(1'b0),
|
||||
.PCIN(48'b0),
|
||||
.ACOUT(),
|
||||
.BCOUT(),
|
||||
.CARRYCASCOUT(),
|
||||
.MULTSIGNOUT(),
|
||||
.PCOUT()
|
||||
);
|
||||
|
||||
// DSP48E1 for Q-channel mixer (adc_signed * sin_out)
|
||||
DSP48E1 #(
|
||||
.A_INPUT("DIRECT"),
|
||||
.B_INPUT("DIRECT"),
|
||||
.USE_DPORT("FALSE"),
|
||||
.USE_MULT("MULTIPLY"),
|
||||
.USE_SIMD("ONE48"),
|
||||
.AREG(1),
|
||||
.BREG(1),
|
||||
.MREG(1),
|
||||
.PREG(1),
|
||||
.ADREG(0),
|
||||
.ACASCREG(1),
|
||||
.BCASCREG(1),
|
||||
.ALUMODEREG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSELREG(0),
|
||||
.CREG(0),
|
||||
.DREG(0),
|
||||
.INMODEREG(0),
|
||||
.OPMODEREG(0),
|
||||
.AUTORESET_PATDET("NO_RESET"),
|
||||
.MASK(48'h3fffffffffff),
|
||||
.PATTERN(48'h000000000000),
|
||||
.SEL_MASK("MASK"),
|
||||
.SEL_PATTERN("PATTERN"),
|
||||
.USE_PATTERN_DETECT("NO_PATDET")
|
||||
) dsp_mixer_q (
|
||||
.CLK(clk_400m),
|
||||
.RSTA(!reset_n),
|
||||
.RSTB(!reset_n),
|
||||
.RSTM(!reset_n),
|
||||
.RSTP(!reset_n),
|
||||
.RSTALLCARRYIN(1'b0),
|
||||
.RSTALUMODE(1'b0),
|
||||
.RSTCTRL(1'b0),
|
||||
.RSTC(1'b0),
|
||||
.RSTD(1'b0),
|
||||
.RSTINMODE(1'b0),
|
||||
.CEA1(1'b0),
|
||||
.CEA2(1'b1),
|
||||
.CEB1(1'b0),
|
||||
.CEB2(1'b1),
|
||||
.CEM(1'b1),
|
||||
.CEP(1'b1), // P register clock enable (PREG=1)
|
||||
.CEAD(1'b0),
|
||||
.CEALUMODE(1'b0),
|
||||
.CECARRYIN(1'b0),
|
||||
.CECTRL(1'b0),
|
||||
.CEC(1'b0),
|
||||
.CED(1'b0),
|
||||
.CEINMODE(1'b0),
|
||||
.A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}),
|
||||
.B({{2{sin_out[15]}}, sin_out}),
|
||||
.C(48'b0),
|
||||
.D(25'b0),
|
||||
.CARRYIN(1'b0),
|
||||
.OPMODE(7'b0000101),
|
||||
.ALUMODE(4'b0000),
|
||||
.INMODE(5'b00000),
|
||||
.CARRYINSEL(3'b000),
|
||||
.P(dsp_p_q),
|
||||
.PATTERNDETECT(),
|
||||
.PATTERNBDETECT(),
|
||||
.OVERFLOW(),
|
||||
.UNDERFLOW(),
|
||||
.CARRYOUT(),
|
||||
.ACIN(30'b0),
|
||||
.BCIN(18'b0),
|
||||
.CARRYCASCIN(1'b0),
|
||||
.MULTSIGNIN(1'b0),
|
||||
.PCIN(48'b0),
|
||||
.ACOUT(),
|
||||
.BCOUT(),
|
||||
.CARRYCASCOUT(),
|
||||
.MULTSIGNOUT(),
|
||||
.PCOUT()
|
||||
);
|
||||
|
||||
// Extract the multiply result from DSP48E1 P output
|
||||
// adc_signed is 18 bits, NCO is 16 bits → product is 34 bits (bits [33:0] of P)
|
||||
wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg = dsp_p_i[MIXER_WIDTH+NCO_WIDTH-1:0];
|
||||
wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WIDTH-1:0];
|
||||
|
||||
`endif
|
||||
|
||||
// ============================================================================
|
||||
// Post-DSP48E1 output stage: force_saturation override + overflow detection
|
||||
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
|
||||
// polluting the critical input path with extra logic
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
mixed_i <= 0;
|
||||
mixed_q <= 0;
|
||||
mixed_valid <= 0;
|
||||
mixer_overflow_i <= 0;
|
||||
mixer_overflow_q <= 0;
|
||||
saturation_count <= 0;
|
||||
overflow_detected <= 0;
|
||||
end else if (dsp_valid_pipe[2]) begin
|
||||
// Force saturation for testing (applied after DSP output, not on input path)
|
||||
if (force_saturation_sync) begin
|
||||
mixed_i <= 34'h1FFFFFFFF;
|
||||
mixed_q <= 34'h200000000;
|
||||
mixer_overflow_i <= 1'b1;
|
||||
mixer_overflow_q <= 1'b1;
|
||||
end else begin
|
||||
// Normal path: take DSP48E1 multiply result
|
||||
mixed_i <= mult_i_reg;
|
||||
mixed_q <= mult_q_reg;
|
||||
|
||||
// Overflow detection on current cycle's multiply result
|
||||
mixer_overflow_i <= (mult_i_reg > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
|
||||
(mult_i_reg < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
|
||||
mixer_overflow_q <= (mult_q_reg > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
|
||||
(mult_q_reg < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
|
||||
end
|
||||
|
||||
mixed_valid <= 1;
|
||||
|
||||
if (mixer_overflow_i || mixer_overflow_q) begin
|
||||
saturation_count <= saturation_count + 1;
|
||||
overflow_detected <= 1'b1;
|
||||
end else begin
|
||||
overflow_detected <= 1'b0;
|
||||
end
|
||||
|
||||
end else begin
|
||||
mixed_valid <= 0;
|
||||
mixer_overflow_i <= 0;
|
||||
mixer_overflow_q <= 0;
|
||||
overflow_detected <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
|
||||
@@ -11,11 +11,38 @@ module nco_400m_enhanced (
|
||||
output reg dds_ready
|
||||
);
|
||||
|
||||
// Phase accumulator with registered outputs for better timing
|
||||
reg [31:0] phase_accumulator;
|
||||
reg [31:0] phase_accumulator_reg;
|
||||
// ============================================================================
|
||||
// 4-stage pipelined NCO for 400 MHz timing closure
|
||||
//
|
||||
// Stage 1: Phase accumulator update (DSP48E1 in P=P+C mode) + offset addition
|
||||
// DSP48E1 does: P_reg <= P_reg + C_port (frequency_tuning_word)
|
||||
// The P register output IS the phase accumulator — no CARRY4 chain.
|
||||
// phase_with_offset = P_output + {phase_offset, 16'b0} (registered)
|
||||
// Stage 2: LUT address decode + LUT read → register abs values + quadrant
|
||||
// Stage 3: Compute negations from registered abs values → register neg values
|
||||
// (CARRY4 x4 chain has registered inputs, fits in 2.5ns easily)
|
||||
// Stage 4: Quadrant sign application → sin_out, cos_out (pure MUX, no arith)
|
||||
//
|
||||
// Total latency: 4 cycles from phase_valid to sin/cos output
|
||||
// Max logic levels per stage: Stage 1=DSP48E1(internal), Stage 2=2(LUT3+LUT6),
|
||||
// Stage 3=4(CARRY4 chain), Stage 4=1(MUX)
|
||||
// ============================================================================
|
||||
|
||||
// Phase accumulator — DSP48E1 P output provides the accumulated phase
|
||||
// In simulation: behavioral reg. In synthesis: DSP48E1 P[31:0].
|
||||
reg [31:0] phase_with_offset;
|
||||
reg phase_valid_delayed;
|
||||
|
||||
// Stage 2 pipeline registers: LUT output + quadrant
|
||||
reg [15:0] sin_abs_reg, cos_abs_reg;
|
||||
reg [1:0] quadrant_reg;
|
||||
|
||||
// Stage 3 pipeline registers: pre-computed negations + abs copies + quadrant
|
||||
reg signed [15:0] sin_neg_reg, cos_neg_reg;
|
||||
reg [15:0] sin_abs_reg2, cos_abs_reg2; // Pass-through for Stage 4 MUX
|
||||
reg [1:0] quadrant_reg2; // Pass-through for Stage 4 MUX
|
||||
|
||||
// Valid pipeline: tracks 4-stage latency
|
||||
reg [3:0] valid_pipe;
|
||||
|
||||
// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
|
||||
wire [7:0] lut_address = phase_with_offset[31:24];
|
||||
@@ -51,61 +78,229 @@ initial begin
|
||||
sin_lut[60] = 16'h7F61; sin_lut[61] = 16'h7FA6; sin_lut[62] = 16'h7FD8; sin_lut[63] = 16'h7FF5;
|
||||
end
|
||||
|
||||
// Quadrant determination
|
||||
wire [1:0] quadrant = lut_address[7:6]; // 00: Q1, 01: Q2, 10: Q3, 11: Q4
|
||||
wire [5:0] lut_index = (quadrant[1] ? ~lut_address[5:0] : lut_address[5:0]); // Mirror for Q2/Q3
|
||||
// Combinational: quadrant determination and LUT index (feeds Stage 2 registers)
|
||||
wire [1:0] quadrant_w = lut_address[7:6];
|
||||
wire [5:0] lut_index = (quadrant_w[0] ^ quadrant_w[1]) ? ~lut_address[5:0] : lut_address[5:0];
|
||||
|
||||
// Sine and cosine calculation with quadrant mapping
|
||||
wire [15:0] sin_abs = sin_lut[lut_index];
|
||||
wire [15:0] cos_abs = sin_lut[63 - lut_index]; // Cosine is phase-shifted sine
|
||||
// Combinational LUT read (will be registered in Stage 2)
|
||||
wire [15:0] sin_abs_w = sin_lut[lut_index];
|
||||
wire [15:0] cos_abs_w = sin_lut[63 - lut_index];
|
||||
|
||||
// ============================================================================
|
||||
// Stage 1: Phase accumulator (DSP48E1) + offset addition (fabric register)
|
||||
//
|
||||
// The phase accumulator is the critical path bottleneck: a 32-bit addition
|
||||
// requires 8 CARRY4 stages in fabric (2.826 ns > 2.5 ns budget at 400 MHz).
|
||||
// Solution: Use DSP48E1 in P = P + C accumulate mode.
|
||||
// - C-port carries frequency_tuning_word (zero-extended to 48 bits)
|
||||
// - CREG=1 registers the tuning word inside the DSP
|
||||
// - PREG=1 registers the accumulator output (P = P + C each cycle)
|
||||
// - The DSP48E1 48-bit ALU performs the add internally at full speed
|
||||
// - Only P[31:0] is used (32-bit phase accumulator)
|
||||
//
|
||||
// phase_with_offset is computed in fabric: DSP48E1 P output + {phase_offset, 16'b0}
|
||||
// This is OK because both operands are registered (P is PREG output, phase_offset
|
||||
// is a stable input), and the result feeds Stage 2 LUT which is also registered.
|
||||
// ============================================================================
|
||||
|
||||
`ifdef SIMULATION
|
||||
// ---- Behavioral model for Icarus Verilog simulation ----
|
||||
// Mimics DSP48E1 accumulator: P <= P + C, with CREG=1, PREG=1
|
||||
reg [31:0] phase_accumulator;
|
||||
|
||||
// Pipeline stage for better timing
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
phase_accumulator <= 32'h00000000;
|
||||
phase_accumulator_reg <= 32'h00000000;
|
||||
phase_with_offset <= 32'h00000000;
|
||||
phase_valid_delayed <= 1'b0;
|
||||
dds_ready <= 1'b0;
|
||||
end else if (phase_valid) begin
|
||||
phase_accumulator <= phase_accumulator + frequency_tuning_word;
|
||||
phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
|
||||
end
|
||||
end
|
||||
|
||||
`else
|
||||
// ---- DSP48E1 phase accumulator for Vivado synthesis ----
|
||||
// P = P + C mode: accumulates frequency_tuning_word each clock cycle
|
||||
// Uses 1 DSP48E1 (total design: 5 of 240 available = 2.08%)
|
||||
wire [47:0] phase_accum_p; // DSP48E1 P output (48 bits, use [31:0])
|
||||
|
||||
DSP48E1 #(
|
||||
// Feature control
|
||||
.A_INPUT("DIRECT"),
|
||||
.B_INPUT("DIRECT"),
|
||||
.USE_DPORT("FALSE"),
|
||||
.USE_MULT("NONE"), // No multiplier — pure ALU accumulate
|
||||
.USE_SIMD("ONE48"),
|
||||
// Pipeline registers
|
||||
.AREG(0), // A-port unused for accumulate
|
||||
.BREG(0), // B-port unused for accumulate
|
||||
.CREG(1), // Register frequency_tuning_word on C-port
|
||||
.MREG(0), // No multiplier
|
||||
.PREG(1), // P register IS the phase accumulator
|
||||
.ADREG(0),
|
||||
.ACASCREG(0),
|
||||
.BCASCREG(0),
|
||||
.ALUMODEREG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSELREG(0),
|
||||
.DREG(0),
|
||||
.INMODEREG(0),
|
||||
.OPMODEREG(0),
|
||||
// Pattern detector (unused)
|
||||
.AUTORESET_PATDET("NO_RESET"),
|
||||
.MASK(48'h3fffffffffff),
|
||||
.PATTERN(48'h000000000000),
|
||||
.SEL_MASK("MASK"),
|
||||
.SEL_PATTERN("PATTERN"),
|
||||
.USE_PATTERN_DETECT("NO_PATDET")
|
||||
) dsp_phase_accum (
|
||||
// Clock and reset
|
||||
.CLK(clk_400m),
|
||||
.RSTA(1'b0),
|
||||
.RSTB(1'b0),
|
||||
.RSTM(1'b0),
|
||||
.RSTP(!reset_n), // Reset P register (phase accumulator) on !reset_n
|
||||
.RSTC(!reset_n), // Reset C register (tuning word) on !reset_n
|
||||
.RSTALLCARRYIN(1'b0),
|
||||
.RSTALUMODE(1'b0),
|
||||
.RSTCTRL(1'b0),
|
||||
.RSTD(1'b0),
|
||||
.RSTINMODE(1'b0),
|
||||
// Clock enables
|
||||
.CEA1(1'b0),
|
||||
.CEA2(1'b0),
|
||||
.CEB1(1'b0),
|
||||
.CEB2(1'b0),
|
||||
.CEC(1'b1), // Always register C (tuning word updates)
|
||||
.CEM(1'b0),
|
||||
.CEP(phase_valid), // Only accumulate when phase_valid is asserted
|
||||
.CEAD(1'b0),
|
||||
.CEALUMODE(1'b0),
|
||||
.CECARRYIN(1'b0),
|
||||
.CECTRL(1'b0),
|
||||
.CED(1'b0),
|
||||
.CEINMODE(1'b0),
|
||||
// Data ports
|
||||
.A(30'b0), // Unused for P = P + C
|
||||
.B(18'b0), // Unused for P = P + C
|
||||
.C({16'b0, frequency_tuning_word}), // Zero-extend 32-bit FTW to 48 bits
|
||||
.D(25'b0),
|
||||
.CARRYIN(1'b0),
|
||||
// Control ports
|
||||
.OPMODE(7'b0010011), // Z=P (010), Y=0 (00), X=C_reg (11) → P = P + C
|
||||
.ALUMODE(4'b0000), // Z + X + Y + CIN (standard add)
|
||||
.INMODE(5'b00000),
|
||||
.CARRYINSEL(3'b000),
|
||||
// Output ports
|
||||
.P(phase_accum_p),
|
||||
.PATTERNDETECT(),
|
||||
.PATTERNBDETECT(),
|
||||
.OVERFLOW(),
|
||||
.UNDERFLOW(),
|
||||
.CARRYOUT(),
|
||||
// Cascade ports (unused)
|
||||
.ACIN(30'b0),
|
||||
.BCIN(18'b0),
|
||||
.CARRYCASCIN(1'b0),
|
||||
.MULTSIGNIN(1'b0),
|
||||
.PCIN(48'b0),
|
||||
.ACOUT(),
|
||||
.BCOUT(),
|
||||
.CARRYCASCOUT(),
|
||||
.MULTSIGNOUT(),
|
||||
.PCOUT()
|
||||
);
|
||||
|
||||
// phase_with_offset: add phase_offset to the DSP48E1 accumulator output
|
||||
// Both operands are registered (phase_accum_p from PREG, phase_offset is stable input)
|
||||
// This fabric add feeds Stage 2 LUT which is also registered — timing is fine
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
phase_with_offset <= 32'h00000000;
|
||||
end else if (phase_valid) begin
|
||||
phase_with_offset <= phase_accum_p[31:0] + {phase_offset, 16'b0};
|
||||
end
|
||||
end
|
||||
|
||||
`endif
|
||||
|
||||
// ============================================================================
|
||||
// Stage 2: LUT read + register absolute values and quadrant
|
||||
// Only LUT decode here — negation is deferred to Stage 3
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sin_abs_reg <= 16'h0000;
|
||||
cos_abs_reg <= 16'h7FFF;
|
||||
quadrant_reg <= 2'b00;
|
||||
end else if (valid_pipe[0]) begin
|
||||
sin_abs_reg <= sin_abs_w;
|
||||
cos_abs_reg <= cos_abs_w;
|
||||
quadrant_reg <= quadrant_w;
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Stage 3: Compute negations from registered abs values
|
||||
// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
|
||||
// Also pass through abs values and quadrant for Stage 4
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sin_neg_reg <= 16'h0000;
|
||||
cos_neg_reg <= -16'h7FFF;
|
||||
sin_abs_reg2 <= 16'h0000;
|
||||
cos_abs_reg2 <= 16'h7FFF;
|
||||
quadrant_reg2 <= 2'b00;
|
||||
end else if (valid_pipe[1]) begin
|
||||
sin_neg_reg <= -sin_abs_reg;
|
||||
cos_neg_reg <= -cos_abs_reg;
|
||||
sin_abs_reg2 <= sin_abs_reg;
|
||||
cos_abs_reg2 <= cos_abs_reg;
|
||||
quadrant_reg2 <= quadrant_reg;
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Stage 4: Quadrant sign application → final sin/cos output
|
||||
// Uses pre-computed negated values from Stage 3 — pure MUX, no arithmetic
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sin_out <= 16'h0000;
|
||||
cos_out <= 16'h7FFF;
|
||||
end else if (valid_pipe[2]) begin
|
||||
case (quadrant_reg2)
|
||||
2'b00: begin // Quadrant I: sin+, cos+
|
||||
sin_out <= sin_abs_reg2;
|
||||
cos_out <= cos_abs_reg2;
|
||||
end
|
||||
2'b01: begin // Quadrant II: sin+, cos-
|
||||
sin_out <= sin_abs_reg2;
|
||||
cos_out <= cos_neg_reg;
|
||||
end
|
||||
2'b10: begin // Quadrant III: sin-, cos-
|
||||
sin_out <= sin_neg_reg;
|
||||
cos_out <= cos_neg_reg;
|
||||
end
|
||||
2'b11: begin // Quadrant IV: sin-, cos+
|
||||
sin_out <= sin_neg_reg;
|
||||
cos_out <= cos_abs_reg2;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Valid pipeline and dds_ready (4-stage latency)
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
valid_pipe <= 4'b0000;
|
||||
dds_ready <= 1'b0;
|
||||
end else begin
|
||||
phase_valid_delayed <= phase_valid;
|
||||
|
||||
if (phase_valid) begin
|
||||
// Update phase accumulator with dithered frequency tuning word
|
||||
phase_accumulator <= phase_accumulator + frequency_tuning_word;
|
||||
phase_accumulator_reg <= phase_accumulator;
|
||||
|
||||
// Apply phase offset
|
||||
phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
|
||||
dds_ready <= 1'b1;
|
||||
end else begin
|
||||
dds_ready <= 1'b0;
|
||||
end
|
||||
|
||||
// Generate outputs with one cycle delay for pipelining
|
||||
if (phase_valid_delayed) begin
|
||||
// Calculate sine and cosine with proper quadrant signs
|
||||
case (quadrant)
|
||||
2'b00: begin // Quadrant I: sin+, cos+
|
||||
sin_out <= sin_abs;
|
||||
cos_out <= cos_abs;
|
||||
end
|
||||
2'b01: begin // Quadrant II: sin+, cos-
|
||||
sin_out <= sin_abs;
|
||||
cos_out <= -cos_abs;
|
||||
end
|
||||
2'b10: begin // Quadrant III: sin-, cos-
|
||||
sin_out <= -sin_abs;
|
||||
cos_out <= -cos_abs;
|
||||
end
|
||||
2'b11: begin // Quadrant IV: sin-, cos+
|
||||
sin_out <= -sin_abs;
|
||||
cos_out <= cos_abs;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
valid_pipe <= {valid_pipe[2:0], phase_valid};
|
||||
dds_ready <= valid_pipe[3];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@@ -191,7 +191,7 @@ BUFG bufg_ft601 (
|
||||
);
|
||||
|
||||
// Reset synchronization (clk_100m domain)
|
||||
reg [1:0] reset_sync;
|
||||
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;
|
||||
always @(posedge clk_100m_buf or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
reset_sync <= 2'b00;
|
||||
@@ -204,7 +204,7 @@ assign sys_reset_n = reset_sync[1];
|
||||
// Reset synchronization (clk_120m_dac domain)
|
||||
// Ensures reset deassertion is synchronous to the DAC clock,
|
||||
// preventing recovery/removal timing violations on 120 MHz FFs.
|
||||
reg [1:0] reset_sync_120m;
|
||||
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_120m;
|
||||
always @(posedge clk_120m_dac_buf or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
reset_sync_120m <= 2'b00;
|
||||
|
||||
@@ -1,50 +1,50 @@
|
||||
input_sample,output_sample,data_out,data_out_valid
|
||||
5,0,0,1
|
||||
9,1,0,1
|
||||
13,2,0,1
|
||||
17,3,0,1
|
||||
21,4,0,1
|
||||
25,5,0,1
|
||||
29,6,0,1
|
||||
33,7,0,1
|
||||
37,8,118,1
|
||||
41,9,651,1
|
||||
45,10,979,1
|
||||
49,11,1000,1
|
||||
53,12,1000,1
|
||||
57,13,1000,1
|
||||
61,14,1000,1
|
||||
65,15,1000,1
|
||||
69,16,1000,1
|
||||
73,17,1000,1
|
||||
77,18,1000,1
|
||||
81,19,1000,1
|
||||
85,20,1000,1
|
||||
89,21,1000,1
|
||||
93,22,1000,1
|
||||
97,23,1000,1
|
||||
101,24,1000,1
|
||||
105,25,1000,1
|
||||
109,26,1000,1
|
||||
113,27,1000,1
|
||||
117,28,1000,1
|
||||
121,29,1000,1
|
||||
125,30,1000,1
|
||||
129,31,1000,1
|
||||
133,32,1000,1
|
||||
137,33,1000,1
|
||||
141,34,1000,1
|
||||
145,35,1000,1
|
||||
149,36,1000,1
|
||||
153,37,1000,1
|
||||
157,38,1000,1
|
||||
161,39,1000,1
|
||||
165,40,1000,1
|
||||
169,41,1000,1
|
||||
173,42,1000,1
|
||||
177,43,1000,1
|
||||
181,44,1000,1
|
||||
185,45,1000,1
|
||||
189,46,1000,1
|
||||
193,47,1000,1
|
||||
197,48,1000,1
|
||||
6,0,0,1
|
||||
10,1,0,1
|
||||
14,2,0,1
|
||||
18,3,0,1
|
||||
22,4,0,1
|
||||
26,5,0,1
|
||||
30,6,0,1
|
||||
34,7,118,1
|
||||
38,8,651,1
|
||||
42,9,979,1
|
||||
46,10,1000,1
|
||||
50,11,1000,1
|
||||
54,12,1000,1
|
||||
58,13,1000,1
|
||||
62,14,1000,1
|
||||
66,15,1000,1
|
||||
70,16,1000,1
|
||||
74,17,1000,1
|
||||
78,18,1000,1
|
||||
82,19,1000,1
|
||||
86,20,1000,1
|
||||
90,21,1000,1
|
||||
94,22,1000,1
|
||||
98,23,1000,1
|
||||
102,24,1000,1
|
||||
106,25,1000,1
|
||||
110,26,1000,1
|
||||
114,27,1000,1
|
||||
118,28,1000,1
|
||||
122,29,1000,1
|
||||
126,30,1000,1
|
||||
130,31,1000,1
|
||||
134,32,1000,1
|
||||
138,33,1000,1
|
||||
142,34,1000,1
|
||||
146,35,1000,1
|
||||
150,36,1000,1
|
||||
154,37,1000,1
|
||||
158,38,1000,1
|
||||
162,39,1000,1
|
||||
166,40,1000,1
|
||||
170,41,1000,1
|
||||
174,42,1000,1
|
||||
178,43,1000,1
|
||||
182,44,1000,1
|
||||
186,45,1000,1
|
||||
190,46,1000,1
|
||||
194,47,1000,1
|
||||
198,48,1000,1
|
||||
|
||||
|
@@ -5,11 +5,11 @@ sample,data_out
|
||||
3,0
|
||||
4,0
|
||||
5,0
|
||||
6,0
|
||||
7,9
|
||||
8,634
|
||||
9,1513
|
||||
10,341
|
||||
6,9
|
||||
7,634
|
||||
8,1513
|
||||
9,341
|
||||
10,0
|
||||
11,0
|
||||
12,0
|
||||
13,0
|
||||
|
||||
|
@@ -1,400 +1,400 @@
|
||||
input_n,data_in,output_n,data_out
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||||
5,392,0,0
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29,2199,6,0
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33,2477,7,0
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45,3247,10,354
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85,4861,20,3214
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File diff suppressed because it is too large
Load Diff
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||||
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||||
88,26319,-18868,1
|
||||
89,-9512,-31113,1
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||||
91,9512,-31113,1
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||||
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||||
93,-18868,26319,1
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||||
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|
||||
95,-32757,0,1
|
||||
96,-31113,9512,1
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97,18868,26319,1
|
||||
98,26319,-18868,1
|
||||
99,-9512,-31113,1
|
||||
0,0,32767,0
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||||
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||||
2,0,32757,0
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||||
3,31113,-9512,1
|
||||
4,-26319,-18868,1
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
47,-32757,0,1
|
||||
48,-9512,31113,1
|
||||
49,18868,26319,1
|
||||
50,18868,-26319,1
|
||||
51,-9512,-31113,1
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||||
52,0,32757,1
|
||||
53,31113,-9512,1
|
||||
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||||
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||||
56,31113,9512,1
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||||
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||||
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||||
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||||
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|
||||
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||||
62,0,32757,1
|
||||
63,31113,-9512,1
|
||||
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||||
65,-26319,18868,1
|
||||
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|
||||
67,-32757,0,1
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||||
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||||
69,18868,26319,1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
80,18868,-26319,1
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
89,18868,26319,1
|
||||
90,18868,-26319,1
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
97,-32757,0,1
|
||||
98,-9512,31113,1
|
||||
99,18868,26319,1
|
||||
|
||||
|
@@ -1,501 +1,501 @@
|
||||
sample,sin_out,cos_out,dds_ready
|
||||
0,0,32767,1
|
||||
1,0,32757,1
|
||||
2,0,32757,1
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||||
3,804,32728,1
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||||
4,804,32728,1
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||||
5,1608,32678,1
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||||
6,2410,32609,1
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||||
7,2410,32609,1
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||||
8,3212,32521,1
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||||
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||||
10,4011,32412,1
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||||
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||||
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|
||||
13,5602,32137,1
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||||
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|
||||
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||||
16,7179,31785,1
|
||||
17,7962,31580,1
|
||||
18,7962,31580,1
|
||||
19,8739,31356,1
|
||||
20,9512,31113,1
|
||||
21,9512,31113,1
|
||||
22,10278,30852,1
|
||||
23,11039,30571,1
|
||||
24,11039,30571,1
|
||||
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|
||||
26,11793,30273,1
|
||||
27,12539,29956,1
|
||||
28,13279,29621,1
|
||||
29,13279,29621,1
|
||||
30,14010,29268,1
|
||||
31,14732,28898,1
|
||||
32,14732,28898,1
|
||||
33,15446,28510,1
|
||||
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|
||||
35,16151,28105,1
|
||||
36,16846,27683,1
|
||||
37,17530,27245,1
|
||||
38,17530,27245,1
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||||
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|
||||
40,18204,26790,1
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||||
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||||
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|
||||
43,19519,25832,1
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44,20159,25329,1
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||||
45,20787,24811,1
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||||
46,20787,24811,1
|
||||
47,21403,24279,1
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||||
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||||
49,22005,23731,1
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|
||||
51,22594,23170,1
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52,23170,22594,1
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||||
65,27245,17530,1
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||||
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||||
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||||
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||||
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||||
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||||
74,29621,13279,1
|
||||
75,29956,12539,1
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||||
76,29956,12539,1
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||||
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||||
78,30571,11039,1
|
||||
79,30571,11039,1
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||||
80,30852,10278,1
|
||||
81,31113,9512,1
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||||
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||||
85,31580,7962,1
|
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90,32137,5602,1
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92,32412,4011,1
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93,32412,4011,1
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95,32609,2410,1
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||||
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||||
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|
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133,15446,-28510,1
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|
||||
136,16846,-27683,1
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|
||||
138,17530,-27245,1
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||||
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|
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|
||||
147,21403,-24279,1
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|
||||
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||||
150,22594,-23170,1
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151,22594,-23170,1
|
||||
0,0,32767,0
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1,0,32767,0
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||||
2,0,32767,0
|
||||
3,0,32757,0
|
||||
4,0,32757,1
|
||||
5,804,32728,1
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||||
6,804,32728,1
|
||||
7,1608,32678,1
|
||||
8,2410,32609,1
|
||||
9,2410,32609,1
|
||||
10,3212,32521,1
|
||||
11,4011,32412,1
|
||||
12,4011,32412,1
|
||||
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|
||||
14,5602,32137,1
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||||
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|
||||
16,6393,31971,1
|
||||
17,6393,31971,1
|
||||
18,7179,31785,1
|
||||
19,7962,31580,1
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||||
20,7962,31580,1
|
||||
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||||
23,9512,31113,1
|
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|
||||
25,11039,30571,1
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||||
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|
||||
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||||
28,11793,30273,1
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||||
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|
||||
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34,14732,28898,1
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48,20787,24811,1
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54,23170,22594,1
|
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||||
57,24279,21403,1
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||||
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||||
59,24811,20787,1
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||||
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||||
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||||
62,25832,19519,1
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||||
63,26319,18868,1
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||||
64,26790,18204,1
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||||
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|
||||
67,27245,17530,1
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||||
68,27683,16846,1
|
||||
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||||
70,28105,16151,1
|
||||
71,28510,15446,1
|
||||
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||||
73,28898,14732,1
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||||
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||||
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76,29621,13279,1
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||||
77,29956,12539,1
|
||||
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||||
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||||
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||||
87,31580,7962,1
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|
||||
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|
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|
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||||
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||||
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||||
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||||
103,32757,0,1
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
114,32137,-5602,1
|
||||
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|
||||
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|
||||
117,31971,-6393,1
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||||
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|
||||
119,31580,-7962,1
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120,31580,-7962,1
|
||||
121,31356,-8739,1
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|
||||
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||||
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|
||||
126,30571,-11039,1
|
||||
127,30273,-11793,1
|
||||
128,30273,-11793,1
|
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129,29956,-12539,1
|
||||
130,29621,-13279,1
|
||||
131,29621,-13279,1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
137,28105,-16151,1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
142,26790,-18204,1
|
||||
143,26319,-18868,1
|
||||
144,25832,-19519,1
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||||
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|
||||
146,25329,-20159,1
|
||||
147,24811,-20787,1
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||||
148,24811,-20787,1
|
||||
149,24279,-21403,1
|
||||
150,23731,-22005,1
|
||||
151,23731,-22005,1
|
||||
152,23170,-22594,1
|
||||
153,23731,-22005,1
|
||||
154,23731,-22005,1
|
||||
155,24279,-21403,1
|
||||
156,24811,-20787,1
|
||||
157,24811,-20787,1
|
||||
158,25329,-20159,1
|
||||
159,25832,-19519,1
|
||||
160,25832,-19519,1
|
||||
161,26319,-18868,1
|
||||
162,26790,-18204,1
|
||||
163,26790,-18204,1
|
||||
164,27245,-17530,1
|
||||
165,27245,-17530,1
|
||||
166,27683,-16846,1
|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
499,32678,1608,1
|
||||
|
||||
|
@@ -1,201 +1,201 @@
|
||||
sample,sin_out,cos_out
|
||||
0,22594,23170
|
||||
1,26319,18868
|
||||
2,28898,14732
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||||
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|
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|
||||
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|
||||
133,31113,-9512
|
||||
134,32285,-4808
|
||||
135,32757,0
|
||||
136,-32285,-4808
|
||||
137,-31113,-9512
|
||||
138,-28898,-14732
|
||||
139,-26319,-18868
|
||||
140,-23170,-22594
|
||||
141,-18868,-26319
|
||||
142,-14732,-28898
|
||||
143,-9512,-31113
|
||||
144,-4808,-32285
|
||||
145,0,-32757
|
||||
146,-32285,4808
|
||||
147,-31113,9512
|
||||
148,-28898,14732
|
||||
149,-26319,18868
|
||||
150,-23170,22594
|
||||
132,23170,-22594
|
||||
133,18868,-26319
|
||||
134,14732,-28898
|
||||
135,9512,-31113
|
||||
136,4808,-32285
|
||||
137,0,-32757
|
||||
138,-32285,-4808
|
||||
139,-31113,-9512
|
||||
140,-28898,-14732
|
||||
141,-26319,-18868
|
||||
142,-23170,-22594
|
||||
143,-18868,-26319
|
||||
144,-14732,-28898
|
||||
145,-9512,-31113
|
||||
146,-4808,-32285
|
||||
147,0,-32757
|
||||
148,-4808,32285
|
||||
149,-9512,31113
|
||||
150,-14732,28898
|
||||
151,-18868,26319
|
||||
152,-14732,28898
|
||||
153,-9512,31113
|
||||
154,-4808,32285
|
||||
155,0,32757
|
||||
156,4808,32285
|
||||
157,9512,31113
|
||||
158,14732,28898
|
||||
159,18868,26319
|
||||
160,22594,23170
|
||||
161,26319,18868
|
||||
162,28898,14732
|
||||
163,31113,9512
|
||||
164,32285,4808
|
||||
165,32757,0
|
||||
166,4808,-32285
|
||||
167,9512,-31113
|
||||
168,14732,-28898
|
||||
169,18868,-26319
|
||||
170,22594,-23170
|
||||
152,-22594,23170
|
||||
153,-26319,18868
|
||||
154,-28898,14732
|
||||
155,-31113,9512
|
||||
156,-32285,4808
|
||||
157,-32757,0
|
||||
158,4808,32285
|
||||
159,9512,31113
|
||||
160,14732,28898
|
||||
161,18868,26319
|
||||
162,22594,23170
|
||||
163,26319,18868
|
||||
164,28898,14732
|
||||
165,31113,9512
|
||||
166,32285,4808
|
||||
167,32757,0
|
||||
168,32285,-4808
|
||||
169,31113,-9512
|
||||
170,28898,-14732
|
||||
171,26319,-18868
|
||||
172,28898,-14732
|
||||
173,31113,-9512
|
||||
174,32285,-4808
|
||||
175,32757,0
|
||||
176,-32285,-4808
|
||||
177,-31113,-9512
|
||||
178,-28898,-14732
|
||||
179,-26319,-18868
|
||||
180,-23170,-22594
|
||||
181,-18868,-26319
|
||||
182,-14732,-28898
|
||||
183,-9512,-31113
|
||||
184,-4808,-32285
|
||||
185,0,-32757
|
||||
186,-32285,4808
|
||||
187,-31113,9512
|
||||
188,-28898,14732
|
||||
189,-26319,18868
|
||||
190,-23170,22594
|
||||
172,23170,-22594
|
||||
173,18868,-26319
|
||||
174,14732,-28898
|
||||
175,9512,-31113
|
||||
176,4808,-32285
|
||||
177,0,-32757
|
||||
178,-32285,-4808
|
||||
179,-31113,-9512
|
||||
180,-28898,-14732
|
||||
181,-26319,-18868
|
||||
182,-23170,-22594
|
||||
183,-18868,-26319
|
||||
184,-14732,-28898
|
||||
185,-9512,-31113
|
||||
186,-4808,-32285
|
||||
187,0,-32757
|
||||
188,-4808,32285
|
||||
189,-9512,31113
|
||||
190,-14732,28898
|
||||
191,-18868,26319
|
||||
192,-14732,28898
|
||||
193,-9512,31113
|
||||
194,-4808,32285
|
||||
195,0,32757
|
||||
196,4808,32285
|
||||
197,9512,31113
|
||||
198,14732,28898
|
||||
199,18868,26319
|
||||
192,-22594,23170
|
||||
193,-26319,18868
|
||||
194,-28898,14732
|
||||
195,-31113,9512
|
||||
196,-32285,4808
|
||||
197,-32757,0
|
||||
198,4808,32285
|
||||
199,9512,31113
|
||||
|
||||
|
@@ -7,16 +7,16 @@ sample,sin,cos,mag_sq
|
||||
5,31113,9512,1058496913
|
||||
6,32285,4808,1065438089
|
||||
7,32757,0,1073021049
|
||||
8,4808,-32285,1065438089
|
||||
9,9512,-31113,1058496913
|
||||
10,14732,-28898,1052126228
|
||||
11,18868,-26319,1048691185
|
||||
12,22594,-23170,1047337736
|
||||
13,26319,-18868,1048691185
|
||||
14,28898,-14732,1052126228
|
||||
15,31113,-9512,1058496913
|
||||
16,32285,-4808,1065438089
|
||||
17,32757,0,1073021049
|
||||
8,32285,-4808,1065438089
|
||||
9,31113,-9512,1058496913
|
||||
10,28898,-14732,1052126228
|
||||
11,26319,-18868,1048691185
|
||||
12,23170,-22594,1047337736
|
||||
13,18868,-26319,1048691185
|
||||
14,14732,-28898,1052126228
|
||||
15,9512,-31113,1058496913
|
||||
16,4808,-32285,1065438089
|
||||
17,0,-32757,1073021049
|
||||
18,-32285,-4808,1065438089
|
||||
19,-31113,-9512,1058496913
|
||||
20,-28898,-14732,1052126228
|
||||
@@ -27,15 +27,15 @@ sample,sin,cos,mag_sq
|
||||
25,-9512,-31113,1058496913
|
||||
26,-4808,-32285,1065438089
|
||||
27,0,-32757,1073021049
|
||||
28,-32285,4808,1065438089
|
||||
29,-31113,9512,1058496913
|
||||
30,-28898,14732,1052126228
|
||||
31,-26319,18868,1048691185
|
||||
32,-23170,22594,1047337736
|
||||
33,-18868,26319,1048691185
|
||||
34,-14732,28898,1052126228
|
||||
35,-9512,31113,1058496913
|
||||
36,-4808,32285,1065438089
|
||||
37,0,32757,1073021049
|
||||
28,-4808,32285,1065438089
|
||||
29,-9512,31113,1058496913
|
||||
30,-14732,28898,1052126228
|
||||
31,-18868,26319,1048691185
|
||||
32,-22594,23170,1047337736
|
||||
33,-26319,18868,1048691185
|
||||
34,-28898,14732,1052126228
|
||||
35,-31113,9512,1058496913
|
||||
36,-32285,4808,1065438089
|
||||
37,-32757,0,1073021049
|
||||
38,4808,32285,1065438089
|
||||
39,9512,31113,1058496913
|
||||
|
||||
|
@@ -259,16 +259,16 @@ module tb_nco_400m;
|
||||
#1;
|
||||
sin_before_gate = sin_out;
|
||||
|
||||
// Deassert phase_valid
|
||||
// Deassert phase_valid — with 4-stage pipeline, dds_ready has 5-cycle latency
|
||||
phase_valid = 0;
|
||||
@(posedge clk_400m); #1;
|
||||
repeat (6) @(posedge clk_400m); #1;
|
||||
check(dds_ready === 1'b0, "dds_ready deasserts when phase_valid=0");
|
||||
|
||||
repeat (10) @(posedge clk_400m);
|
||||
|
||||
// Re-enable
|
||||
// Re-enable — wait for pipeline to refill (5 cycles)
|
||||
phase_valid = 1;
|
||||
@(posedge clk_400m); #1;
|
||||
repeat (6) @(posedge clk_400m); #1;
|
||||
check(dds_ready === 1'b1, "dds_ready re-asserts when phase_valid=1");
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
@@ -285,8 +285,8 @@ module tb_nco_400m;
|
||||
frequency_tuning_word = FTW_10MHZ;
|
||||
phase_valid = 1;
|
||||
|
||||
// Skip pipeline warmup
|
||||
repeat (3) @(posedge clk_400m);
|
||||
// Skip pipeline warmup (4-stage pipeline + 1 for dds_ready)
|
||||
repeat (5) @(posedge clk_400m);
|
||||
|
||||
mag_sq_min = 32'hFFFFFFFF;
|
||||
mag_sq_max = 32'h00000000;
|
||||
|
||||
@@ -63,9 +63,9 @@ reg ft601_data_oe; // Output enable for bidirectional data bus
|
||||
// Even though both are 100 MHz, they are asynchronous clocks and need synchronization.
|
||||
|
||||
// 2-stage synchronizers for valid signals
|
||||
reg [1:0] range_valid_sync;
|
||||
reg [1:0] doppler_valid_sync;
|
||||
reg [1:0] cfar_valid_sync;
|
||||
(* ASYNC_REG = "TRUE" *) reg [1:0] range_valid_sync;
|
||||
(* ASYNC_REG = "TRUE" *) reg [1:0] doppler_valid_sync;
|
||||
(* ASYNC_REG = "TRUE" *) reg [1:0] cfar_valid_sync;
|
||||
|
||||
// Synchronized data captures (registered in ft601_clk_in domain)
|
||||
reg [31:0] range_profile_cap;
|
||||
|
||||
Reference in New Issue
Block a user