From c91e4b425201f7c5eb3c37e36fffd1c929d9cc7d Mon Sep 17 00:00:00 2001 From: NawfalMotii79 Date: Thu, 2 Apr 2026 00:56:29 +0100 Subject: [PATCH] Delete index.html --- index.html | 643 ----------------------------------------------------- 1 file changed, 643 deletions(-) delete mode 100644 index.html diff --git a/index.html b/index.html deleted file mode 100644 index 521473d..0000000 --- a/index.html +++ /dev/null @@ -1,643 +0,0 @@ - - - - - - - - - AERIS-10 | Open Source Phased Array Radar System - - - - - -
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AERIS-10 Open Source
Phased Array Radar

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A low-cost, hackable 10.5 GHz phased array radar system with Pulse LFM modulation. Designed for researchers, drone developers, and serious SDR enthusiasts.

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- πŸ”“ Open Source - πŸ“‘ 10.5 GHz - 🎯 3km / 20km Range - πŸ”„ Electronic Beam Steering -
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Project Overview

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Democratizing radar technology through open-source hardware and software

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🎯
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Purpose-Built

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Designed for researchers, drone developers, and SDR enthusiasts who need a capable, hackable radar platform.

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100% Open Source

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Complete schematics, PCB layouts, firmware, and software available for modification and learning.

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Real-Time Processing

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FPGA-based signal processing for pulse compression, Doppler FFT, MTI, and CFAR detection.

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GPS & IMU Integrated

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Real-time position tracking, attitude correction, and map visualization for geolocated targets.

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Technical Specifications

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Two versions available to match your range requirements

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SpecificationAERIS-10N (Nexus)AERIS-10X (Extended)
Frequency10.5 GHz10.5 GHz
Max Range3 km20 km
Antenna Type8Γ—16 Patch Array32Γ—16 Slotted Waveguide
Beam SteeringElectronic (Β±45Β°)Electronic (Β±45Β°)
Mechanical Scan360Β° (stepper motor)360Β° (stepper motor)
Output Power~1W10W (GaN amplifier)
ProcessingFPGA + STM32FPGA + STM32
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System Architecture

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Modular design with specialized components for optimal performance

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-β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”
-β”‚                      Antenna Array                           β”‚
-β”‚         (8x16 patch / 32x16 slotted waveguide)              β”‚
-β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”¬β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜
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-β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”
-β”‚                     Main Board                               β”‚
-β”‚  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”‚
-β”‚  β”‚  XC7A100T     β”‚  β”‚  STM32F746   β”‚  β”‚  16x ADTR1107   β”‚   β”‚
-β”‚  β”‚  FPGA         β”‚  β”‚  MCU         β”‚  β”‚  Front End      β”‚   β”‚
-β”‚  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β”‚
-β”‚  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”‚
-β”‚  β”‚  4x ADAR1000  β”‚  β”‚  2x ADF4382  β”‚  β”‚  2x LT5552      β”‚   β”‚
-β”‚  β”‚  Phase Shift  β”‚  β”‚  Synthesizersβ”‚  β”‚  Mixers         β”‚   β”‚
-β”‚  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β”‚
-β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”¬β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜
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-β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”
-β”‚                  Support Modules                             β”‚
-β”‚  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”‚
-β”‚  β”‚  AD9523-1     β”‚  β”‚  GPS Module  β”‚  β”‚  GY-85 IMU      β”‚   β”‚
-β”‚  β”‚  Clock Gen    β”‚  β”‚              β”‚  β”‚                 β”‚   β”‚
-β”‚  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β”‚
-β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜
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πŸ“‘ Power Management Board

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Supplies all necessary voltage levels with proper filtering and sequencing (controlled by microcontroller).

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⏱️ Frequency Synthesizer Board

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High-performance AD9523-1 low jitter clock generator with phase-aligned references for RX/TX, DAC, ADC, and FPGA.

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πŸ”„ Main Board Components

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DAC for chirp generation, LT5552 mixers, ADAR1000 phase shifters (4x), ADTR1107 front-end chips (16x).

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πŸŽ›οΈ XC7A100T FPGA

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Handles PLFM chirp generation, ADC data read, AGC, I/Q down-conversion, decimation, filtering, FFT, pulse compression, Doppler, MTI & CFAR processing.

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βš™οΈ STM32F746 Microcontroller

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Power sequencing, FPGA communication, peripheral configuration (clock generator, synthesizers, phase shifters, GPS, IMU, barometer, stepper motor, sensors).

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πŸ”Š Power Amplifier Boards (10X only)

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10W QPA2962 GaN amplifier for extended range capability.

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Current Status

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Alpha prototype - Actively seeking contributors and beta testers

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βœ… Working Features

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  • Beam formation from 16Γ—8 array
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  • Electronic steering Β±45Β° elevation
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  • Pulse LFM generation and reception
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  • Basic target detection to 1km
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  • Full FPGA processing pipeline
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  • Pulse compression & Doppler processing
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  • MTI & CFAR detection
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🚧 In Progress

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  • Python GUI-based radar processing
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  • Multi-board synchronization
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  • Extended range testing
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  • Crowdfunding campaign
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  • Documentation & assembly guides
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Get Involved

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Join the open-source radar revolution

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🀝 We're Actively Seeking

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- πŸŽ“ University Researchers - 🚁 Drone Startups - πŸ”§ Advanced Makers - πŸ“‘ RF Engineers - πŸ–₯️ FPGA Developers - 🐍 Python/C++ Developers -
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πŸ“¬ Connect With Us

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Documentation

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Everything you need to build, modify, and operate the AERIS-10 radar

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πŸ“˜ Hardware Design Guide

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Schematics, PCB layouts, BOM, and assembly instructions.

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πŸ’Ύ Firmware Development

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STM32 firmware and FPGA bitstream programming guide.

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πŸ”¬ Signal Processing

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Detailed explanation of the FPGA processing pipeline.

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🐍 Python SDK

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GUI and API reference for data visualization and control.

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βš™οΈ Calibration Guide

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Step-by-step calibration procedures for optimal performance.

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πŸ› οΈ Troubleshooting

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Common issues and solutions.

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