Fix synthesis blockers in 9 RTL files for Vivado compatibility

Guard all $display/$error/$time calls with ifdef SIMULATION in: - chirp_memory_loader_param.v (initial + always block debug prints) - cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block) - ddc_400m.v (FIR/baseband debug monitor block) - fft_1024_inverse.v (IFFT config debug block) - matched_filter_multi_segment.v (16 state machine displays + monitor) - nco_400m_enhanced.v (initial block debug print) - radar_receiver_final.v (frame/chirp counter displays) Replace SystemVerilog constructs with Verilog-2001: - usb_data_interface.v (typedef enum -> localparam + reg) - usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
2026-03-15 14:53:35 +02:00
parent f5a3394f23
commit c871281f1e
9 changed files with 236 additions and 159 deletions
@@ -31,45 +31,57 @@ module chirp_memory_loader_param #(

 // Initialize memory
 integer i;
-reg [799:0] debug_msg;

 initial begin
+    `ifdef SIMULATION
    if (DEBUG) begin
        $display("[MEM] Starting memory initialization for 4 long chirp segments");
    end
+    `endif
    
    // === LOAD LONG CHIRP - 4 SEGMENTS ===
    // Segment 0 (addresses 0-1023)
    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 1023);
    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 1023);
+    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-1023)");
+    `endif
    
    // Segment 1 (addresses 1024-2047)
    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 1024, 2047);
    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 1024, 2047);
+    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (1024-2047)");
+    `endif
    
    // Segment 2 (addresses 2048-3071)
    $readmemh(LONG_I_FILE_SEG2, long_chirp_i, 2048, 3071);
    $readmemh(LONG_Q_FILE_SEG2, long_chirp_q, 2048, 3071);
+    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded long chirp segment 2 (2048-3071)");
+    `endif
    
    // Segment 3 (addresses 3072-4095)
    $readmemh(LONG_I_FILE_SEG3, long_chirp_i, 3072, 4095);
    $readmemh(LONG_Q_FILE_SEG3, long_chirp_q, 3072, 4095);
+    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded long chirp segment 3 (3072-4095)");
+    `endif
    
    // === LOAD SHORT CHIRP ===
    // Load first 50 samples (0-49)
    $readmemh(SHORT_I_FILE, short_chirp_i);
    $readmemh(SHORT_Q_FILE, short_chirp_q);
+    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
+    `endif
    
    // Zero pad remaining 974 samples (50-1023)
    for (i = 50; i < 1024; i = i + 1) begin
        short_chirp_i[i] = 16'h0000;
        short_chirp_q[i] = 16'h0000;
    end
+    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-1023");
    
    // === VERIFICATION ===
@@ -87,6 +99,7 @@ initial begin
        $display("  Short[49]:   I=%h Q=%h", short_chirp_i[49], short_chirp_q[49]);
        $display("  Short[50]:   I=%h Q=%h (zero-padded)", short_chirp_i[50], short_chirp_q[50]);
    end
+    `endif
 end

 // Memory access logic
@@ -105,20 +118,24 @@ always @(posedge clk or negedge reset_n) begin
                ref_i <= long_chirp_i[long_addr];
                ref_q <= long_chirp_q[long_addr];
                
+                `ifdef SIMULATION
                if (DEBUG && $time < 100) begin
                    $display("[MEM @%0t] Long chirp: seg=%b, addr=%d, I=%h, Q=%h",
                            $time, segment_select, long_addr,
                            long_chirp_i[long_addr], long_chirp_q[long_addr]);
                end
+                `endif
            end else begin
                // Short chirp (0-1023)
                ref_i <= short_chirp_i[sample_addr];
                ref_q <= short_chirp_q[sample_addr];
                
+                `ifdef SIMULATION
                if (DEBUG && $time < 100) begin
                    $display("[MEM @%0t] Short chirp: addr=%d, I=%h, Q=%h",
                            $time, sample_addr, short_chirp_i[sample_addr], short_chirp_q[sample_addr]);
                end
+                `endif
            end
            mem_ready <= 1'b1;
        end else begin
@@ -97,14 +97,18 @@ always @(posedge clk or negedge reset_n) begin
            overflow_latched <= 1'b1;
            saturation_detected <= 1'b1;
            saturation_event_count <= saturation_event_count + 1;
+            `ifdef SIMULATION
            $display("CIC_SATURATION: Positive overflow at sample %0d", sample_count);
+            `endif
        end else if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) < -(2**35)) begin
            integrator[0] <= -(2**35);
            overflow_detected <= 1'b1;
            overflow_latched <= 1'b1;
            saturation_detected <= 1'b1;
            saturation_event_count <= saturation_event_count + 1;
+            `ifdef SIMULATION
            $display("CIC_SATURATION: Negative overflow at sample %0d", sample_count);
+            `endif
        end else begin
            integrator[0] <= integrator[0] + $signed({{18{data_in[17]}}, data_in});
            overflow_detected <= 1'b0;  // Only clear immediate detection, not latched
@@ -248,15 +252,19 @@ always @(posedge clk or negedge reset_n) begin
            overflow_latched <= 1'b1;
            saturation_detected <= 1'b1;
            saturation_event_count <= saturation_event_count + 1;
+            `ifdef SIMULATION
            $display("CIC_OUTPUT_SAT: TRUE Positive saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d", 
                     comb[STAGES-1], temp_scaled_output, temp_output, 131071);
+            `endif
        end else if (temp_scaled_output < -131072) begin  // -2^17
            data_out <= -131072;
            overflow_latched <= 1'b1;
            saturation_detected <= 1'b1;
            saturation_event_count <= saturation_event_count + 1;
+            `ifdef SIMULATION
            $display("CIC_OUTPUT_SAT: TRUE Negative saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d", 
                     comb[STAGES-1], temp_scaled_output, temp_output, -131072);
+            `endif
        end else begin
            // FIXED: Use the properly truncated 18-bit value
            data_out <= temp_output;
@@ -281,11 +289,13 @@ always @(posedge clk or negedge reset_n) begin
 end

 // Continuous monitoring of saturation status
+`ifdef SIMULATION
 always @(posedge clk) begin
    if (overflow_detected && sample_count < 100) begin
        $display("CIC_OVERFLOW: Immediate detection at sample %0d", sample_count);
    end
 end
+`endif

 // Clear saturation on external reset
 always @(posedge reset_monitors) begin
@@ -340,6 +340,7 @@ assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
 // ============================================================================
 reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;

+`ifdef SIMULATION
 always @(posedge clk_100m) begin
    
    if (fir_valid_i && debug_fir_count < 20) begin
@@ -353,10 +354,12 @@ always @(posedge clk_100m) begin
                 baseband_i, baseband_q, debug_bb_count);
    end
 end
+`endif

 // In ddc_400m.v, add these debug signals:

-// Debug monitoring
+// Debug monitoring (simulation only)
+`ifdef SIMULATION
 reg [31:0] debug_adc_count = 0;
 reg [31:0] debug_baseband_count = 0;

@@ -375,6 +378,7 @@ always @(posedge clk_100m) begin
                 baseband_i, baseband_q, debug_baseband_count, $time);
    end
 end
+`endif


 endmodule
@@ -63,6 +63,7 @@ assign ifft_valid = m_axis_data_tvalid;
 assign m_axis_data_tready = 1'b1;

 // Debug
+`ifdef SIMULATION
 reg [31:0] debug_counter;
 always @(posedge clk) begin
    debug_counter <= debug_counter + 1;
@@ -73,6 +74,7 @@ always @(posedge clk) begin
        end
    end
 end
+`endif

 // IFFT IP instance
 FFT_enhanced ifft_inverse_inst (  // Same IP core, different configuration
@@ -41,7 +41,7 @@ module matched_filter_multi_segment (
 // ========== FIXED PARAMETERS ==========
 parameter BUFFER_SIZE = 1024;
 parameter LONG_CHIRP_SAMPLES = 3000;  // Still 3000 samples total
-parameter SHORT_CHIRP_SAMPLES = 50;   // 0.5µs @ 100MHz
+parameter SHORT_CHIRP_SAMPLES = 50;   // 0.5�s @ 100MHz
 parameter OVERLAP_SAMPLES = 128;      // Standard for 1024-pt FFT
 parameter SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES;  // 896 samples
 parameter DEBUG = 1;                  // Debug output control
@@ -164,11 +164,13 @@ always @(posedge clk or negedge reset_n) begin
                    state <= ST_COLLECT_DATA;
                    total_segments <= use_long_chirp ? LONG_SEGMENTS[2:0] : SHORT_SEGMENTS[2:0];
                    
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] Starting %s chirp, segments: %d",
                             use_long_chirp ? "LONG" : "SHORT", 
                             use_long_chirp ? LONG_SEGMENTS : SHORT_SEGMENTS);
                    $display("[MULTI_SEG_FIXED] Overlap: %d samples, Advance: %d samples",
                             OVERLAP_SAMPLES, SEGMENT_ADVANCE);
+                    `endif
                end
            end
            
@@ -184,10 +186,12 @@ always @(posedge clk or negedge reset_n) begin
                    
                    // Debug: Show first few samples
                    if (chirp_samples_collected < 10 && buffer_write_ptr < 10) begin
+                        `ifdef SIMULATION
                        $display("[MULTI_SEG_FIXED] Store[%0d]: I=%h Q=%h", 
                                 buffer_write_ptr, 
                                 ddc_i[17:2] + ddc_i[1], 
                                 ddc_q[17:2] + ddc_q[1]);
+                        `endif
                    end
                    
                    // Check conditions based on chirp type
@@ -202,21 +206,27 @@ always @(posedge clk or negedge reset_n) begin
                            segment_request <= current_segment[1:0];  // Use lower 2 bits
                            mem_request <= 1;
                            
+                            `ifdef SIMULATION
                            $display("[MULTI_SEG_FIXED] Segment %d ready: %d samples collected",
                                     current_segment, chirp_samples_collected);
+                            `endif
                        end
                        
                        // Check if end of chirp reached
                        if (chirp_samples_collected >= LONG_CHIRP_SAMPLES - 1) begin
                            chirp_complete <= 1;
+                            `ifdef SIMULATION
                            $display("[MULTI_SEG_FIXED] End of long chirp reached");
+                            `endif
                        end
                    end else begin
                        // SHORT CHIRP: Only 50 samples, then zero-pad
                        if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
                            state <= ST_ZERO_PAD;
+                            `ifdef SIMULATION
                            $display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
                                     chirp_samples_collected + 1);
+                            `endif
                        end
                    end
                end
@@ -235,7 +245,9 @@ always @(posedge clk or negedge reset_n) begin
                    state <= ST_WAIT_REF;
                    segment_request <= 0;  // Only one segment for short chirp
                    mem_request <= 1;
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] Zero-pad complete, buffer full");
+                    `endif
                end
            end
            
@@ -248,8 +260,10 @@ always @(posedge clk or negedge reset_n) begin
                    fft_start <= 1;
                    state <= ST_PROCESSING;
                    
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] Reference ready, starting processing segment %d",
                             current_segment);
+                    `endif
                end
            end
            
@@ -266,10 +280,12 @@ always @(posedge clk or negedge reset_n) begin
                    
                    // Debug every 100 samples
                    if (buffer_read_ptr % 100 == 0) begin
+                        `ifdef SIMULATION
                        $display("[MULTI_SEG_FIXED] Processing[%0d]: ADC I=%h Q=%h",
                                buffer_read_ptr,
                                input_buffer_i[buffer_read_ptr],
                                input_buffer_q[buffer_read_ptr]);
+                        `endif
                    end
                    
                    buffer_read_ptr <= buffer_read_ptr + 1;
@@ -282,8 +298,10 @@ always @(posedge clk or negedge reset_n) begin
                    buffer_has_data <= 0;
                    state <= ST_WAIT_FFT;  // CRITICAL: Wait for FFT completion
                    
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] Finished feeding %d samples to FFT, waiting...",
                             BUFFER_SIZE);
+                    `endif
                end
            end
            
@@ -291,8 +309,10 @@ always @(posedge clk or negedge reset_n) begin
                // Wait for the processing chain to complete (2159 cycles latency)
                if (fft_pc_valid) begin
                    state <= ST_OUTPUT;
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] FFT processing complete for segment %d",
                             current_segment);
+                    `endif
                end
            end
            
@@ -303,8 +323,10 @@ always @(posedge clk or negedge reset_n) begin
                pc_valid <= 1;
                segment_done <= 1;
                
+                `ifdef SIMULATION
                $display("[MULTI_SEG_FIXED] Output segment %d: I=%h Q=%h",
                         current_segment, fft_pc_i, fft_pc_q);
+                `endif
                
                // Check if we need more segments
                if (current_segment < total_segments - 1 || !chirp_complete) begin
@@ -312,8 +334,10 @@ always @(posedge clk or negedge reset_n) begin
                end else begin
                    // All segments complete
                    state <= ST_IDLE;
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] All %d segments complete",
                             total_segments);
+                    `endif
                end
            end
            
@@ -334,8 +358,10 @@ always @(posedge clk or negedge reset_n) begin
                    // Start writing after the overlap
                    buffer_write_ptr <= OVERLAP_SAMPLES;
                    
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] Overlap-save: kept %d samples, write_ptr=%d",
                             OVERLAP_SAMPLES, OVERLAP_SAMPLES);
+                    `endif
                end else begin
                    // Short chirp: only one segment
                    buffer_write_ptr <= 0;
@@ -344,8 +370,10 @@ always @(posedge clk or negedge reset_n) begin
                // Continue collecting or finish
                if (!chirp_complete) begin
                    state <= ST_COLLECT_DATA;
+                    `ifdef SIMULATION
                    $display("[MULTI_SEG_FIXED] Starting segment %d/%d",
                             current_segment + 1, total_segments);
+                    `endif
                end else begin
                    state <= ST_IDLE;
                end
@@ -386,6 +414,7 @@ matched_filter_processing_chain m_f_p_c(
 );

 // ========== DEBUG MONITOR ==========
+`ifdef SIMULATION
 reg [31:0] dbg_cycles;
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
@@ -401,6 +430,7 @@ always @(posedge clk or negedge reset_n) begin
        end
    end
 end
+`endif

 // ========== OUTPUT CONNECTIONS ==========
 assign pc_i_w = fft_pc_i;
@@ -109,11 +109,12 @@ always @(posedge clk_400m or negedge reset_n) begin
    end
 end

-// Add this to ensure LUT is properly loaded:
+// Debug verification of LUT initialization (simulation only)
+`ifdef SIMULATION
 initial begin
-    // Wait a small amount of time for LUT initialization
    #10;
    $display("NCO: Sine LUT initialized with %0d entries", 64);
 end
+`endif

 endmodule
@@ -371,15 +371,19 @@ always @(posedge clk or negedge reset_n) begin
        // Detect frame completion
        if (new_chirp_frame) begin
            frame_counter <= frame_counter + 1;
+            `ifdef SIMULATION
            $display("[TOP] Frame %0d started. Previous frame had %0d chirps", 
                     frame_counter, chirps_in_current_frame);
+            `endif
            chirps_in_current_frame <= 0;
        end
        
        // Monitor chirp counter pattern
        if (chirp_counter != chirp_counter_prev) begin
+            `ifdef SIMULATION
            $display("[TOP] chirp_counter: %0d ? %0d", 
                     chirp_counter_prev, chirp_counter);
+            `endif
        end
    end
 end
@@ -43,17 +43,16 @@ localparam FOOTER = 8'h55;
 localparam FT601_DATA_WIDTH = 32;
 localparam FT601_BURST_SIZE = 512;    // Max burst size in bytes

-typedef enum {
-    IDLE,
-    SEND_HEADER,
-    SEND_RANGE_DATA,
-    SEND_DOPPLER_DATA,
-    SEND_DETECTION_DATA,
-    SEND_FOOTER,
-    WAIT_ACK
-} usb_state_t;
+// State definitions (Verilog-2001 compatible)
+localparam [2:0] IDLE                = 3'd0,
+                 SEND_HEADER         = 3'd1,
+                 SEND_RANGE_DATA     = 3'd2,
+                 SEND_DOPPLER_DATA   = 3'd3,
+                 SEND_DETECTION_DATA = 3'd4,
+                 SEND_FOOTER         = 3'd5,
+                 WAIT_ACK            = 3'd6;

-usb_state_t current_state;
+reg [2:0] current_state;
 reg [7:0] byte_counter;
 reg [31:0] data_buffer;
 reg [31:0] ft601_data_out;
@@ -15,7 +15,7 @@ module usb_packet_analyzer (
    output reg packet_valid,
    output reg [7:0] packet_type,
    output reg [31:0] packet_data,
-    output reg [31:0] error_count
+    output wire [31:0] error_count
 );

 // Packet structure
@@ -23,17 +23,15 @@ localparam HEADER = 8'hAA;
 localparam FOOTER = 8'h55;
 localparam HEADER_POS = 24;  // Header in bits [31:24]

-// States
-typedef enum {
-    ST_IDLE,
-    ST_HEADER,
-    ST_RANGE,
-    ST_DOPPLER,
-    ST_DETECTION,
-    ST_FOOTER
-} state_t;
+// States (Verilog-2001 compatible)
+localparam [2:0] ST_IDLE      = 3'd0,
+                 ST_HEADER    = 3'd1,
+                 ST_RANGE     = 3'd2,
+                 ST_DOPPLER   = 3'd3,
+                 ST_DETECTION = 3'd4,
+                 ST_FOOTER    = 3'd5;

-state_t current_state, next_state;
+reg [2:0] current_state, next_state;
 reg [7:0] byte_count;
 reg [31:0] error_reg;
 reg [31:0] packet_count;
@@ -55,8 +53,10 @@ always @(posedge clk or negedge reset_n) begin
                if (usb_wr_strobe && usb_data[31:24] == HEADER) begin
                    current_state <= ST_HEADER;
                    packet_count <= packet_count + 1;
+                    `ifdef SIMULATION
                    $display("[USB_ANALYZER] Packet %0d started at time %0t", 
                             packet_count + 1, $time);
+                    `endif
                end
            end
            
@@ -82,7 +82,9 @@ always @(posedge clk or negedge reset_n) begin
                        packet_data[7:0] <= usb_data[7:0];
                        current_state <= ST_DOPPLER;
                        byte_count <= 8'd0;
+                        `ifdef SIMULATION
                        $display("[USB_ANALYZER] Range data: 0x%08h", packet_data);
+                        `endif
                    end
                end
            end
@@ -96,8 +98,10 @@ always @(posedge clk or negedge reset_n) begin
                        packet_data[15:0] <= usb_data[31:16];   // Doppler imag
                        current_state <= ST_DETECTION;
                        byte_count <= 8'd0;
+                        `ifdef SIMULATION
                        $display("[USB_ANALYZER] Doppler data: real=0x%04h, imag=0x%04h",
                                 packet_data[31:16], packet_data[15:0]);
+                        `endif
                    end
                end
            end
@@ -106,7 +110,9 @@ always @(posedge clk or negedge reset_n) begin
                if (usb_wr_strobe) begin
                    packet_type <= usb_data[0];
                    current_state <= ST_FOOTER;
+                    `ifdef SIMULATION
                    $display("[USB_ANALYZER] Detection: %b", usb_data[0]);
+                    `endif
                end
            end
            
@@ -114,11 +120,15 @@ always @(posedge clk or negedge reset_n) begin
                if (usb_wr_strobe) begin
                    if (usb_data[7:0] == FOOTER) begin
                        packet_valid <= 1'b1;
+                        `ifdef SIMULATION
                        $display("[USB_ANALYZER] Packet %0d valid, footer OK", packet_count);
+                        `endif
                    end else begin
                        error_reg <= error_reg + 1;
+                        `ifdef SIMULATION
                        $error("[USB_ANALYZER] Invalid footer: expected 0x55, got 0x%02h",
                               usb_data[7:0]);
+                        `endif
                    end
                    current_state <= ST_IDLE;
                end