Fix synthesis blockers in 9 RTL files for Vivado compatibility

Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)

9_Firmware/9_2_FPGA/usb_data_interface.v

@@ -43,17 +43,16 @@ localparam FOOTER = 8'h55;
 localparam FT601_DATA_WIDTH = 32;
 localparam FT601_BURST_SIZE = 512;    // Max burst size in bytes
 
-typedef enum {
-    IDLE,
-    SEND_HEADER,
-    SEND_RANGE_DATA,
-    SEND_DOPPLER_DATA,
-    SEND_DETECTION_DATA,
-    SEND_FOOTER,
-    WAIT_ACK
-} usb_state_t;
+// State definitions (Verilog-2001 compatible)
+localparam [2:0] IDLE                = 3'd0,
+                 SEND_HEADER         = 3'd1,
+                 SEND_RANGE_DATA     = 3'd2,
+                 SEND_DOPPLER_DATA   = 3'd3,
+                 SEND_DETECTION_DATA = 3'd4,
+                 SEND_FOOTER         = 3'd5,
+                 WAIT_ACK            = 3'd6;
 
-usb_state_t current_state;
+reg [2:0] current_state;
 reg [7:0] byte_counter;
 reg [31:0] data_buffer;
 reg [31:0] ft601_data_out;