Fix synthesis blockers in 9 RTL files for Vivado compatibility

Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -371,15 +371,19 @@ always @(posedge clk or negedge reset_n) begin
         // Detect frame completion
         if (new_chirp_frame) begin
             frame_counter <= frame_counter + 1;
+            `ifdef SIMULATION
             $display("[TOP] Frame %0d started. Previous frame had %0d chirps", 
                      frame_counter, chirps_in_current_frame);
+            `endif
             chirps_in_current_frame <= 0;
         end
         
         // Monitor chirp counter pattern
         if (chirp_counter != chirp_counter_prev) begin
+            `ifdef SIMULATION
             $display("[TOP] chirp_counter: %0d ? %0d", 
                      chirp_counter_prev, chirp_counter);
+            `endif
         end
     end
 end