Fix synthesis blockers in 9 RTL files for Vivado compatibility

Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)

9_Firmware/9_2_FPGA/nco_400m_enhanced.v

@@ -109,11 +109,12 @@ always @(posedge clk_400m or negedge reset_n) begin
     end
 end
 
-// Add this to ensure LUT is properly loaded:
+// Debug verification of LUT initialization (simulation only)
+`ifdef SIMULATION
 initial begin
-    // Wait a small amount of time for LUT initialization
     #10;
     $display("NCO: Sine LUT initialized with %0d entries", 64);
 end
+`endif
 
 endmodule