Fix synthesis blockers in 9 RTL files for Vivado compatibility

Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)

9_Firmware/9_2_FPGA/fft_1024_inverse.v

@@ -63,6 +63,7 @@ assign ifft_valid = m_axis_data_tvalid;
 assign m_axis_data_tready = 1'b1;
 
 // Debug
+`ifdef SIMULATION
 reg [31:0] debug_counter;
 always @(posedge clk) begin
     debug_counter <= debug_counter + 1;
@@ -73,6 +74,7 @@ always @(posedge clk) begin
         end
     end
 end
+`endif
 
 // IFFT IP instance
 FFT_enhanced ifft_inverse_inst (  // Same IP core, different configuration