Fix synthesis blockers in 9 RTL files for Vivado compatibility

Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -338,43 +338,47 @@ assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
 // ============================================================================
 // Enhanced Debug and Monitoring
 // ============================================================================
-reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
-
-always @(posedge clk_100m) begin
-    
-    if (fir_valid_i && debug_fir_count < 20) begin
-        debug_fir_count <= debug_fir_count + 1;
-        $display("FIR_OUTPUT: fir_i=%6d, fir_q=%6d", fir_i_out, fir_q_out);
-    end
-    
-    if (adc_data_valid_i && adc_data_valid_q && debug_bb_count < 20) begin
-        debug_bb_count <= debug_bb_count + 1;
-        $display("BASEBAND_OUT: i=%6d, q=%6d, count=%0d", 
-                 baseband_i, baseband_q, debug_bb_count);
-    end
-end
+reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
+
+`ifdef SIMULATION
+always @(posedge clk_100m) begin
+    
+    if (fir_valid_i && debug_fir_count < 20) begin
+        debug_fir_count <= debug_fir_count + 1;
+        $display("FIR_OUTPUT: fir_i=%6d, fir_q=%6d", fir_i_out, fir_q_out);
+    end
+    
+    if (adc_data_valid_i && adc_data_valid_q && debug_bb_count < 20) begin
+        debug_bb_count <= debug_bb_count + 1;
+        $display("BASEBAND_OUT: i=%6d, q=%6d, count=%0d", 
+                 baseband_i, baseband_q, debug_bb_count);
+    end
+end
+`endif
 
 // In ddc_400m.v, add these debug signals:
 
-// Debug monitoring
-reg [31:0] debug_adc_count = 0;
-reg [31:0] debug_baseband_count = 0;
-
-always @(posedge clk_400m) begin
-    if (adc_data_valid_i && adc_data_valid_q && debug_adc_count < 10) begin
-        debug_adc_count <= debug_adc_count + 1;
-        $display("DDC_ADC: data=%0d, count=%0d, time=%t", 
-                 adc_data, debug_adc_count, $time);
-    end
-end
-
-always @(posedge clk_100m) begin
-    if (baseband_valid_i && baseband_valid_q && debug_baseband_count < 10) begin
-        debug_baseband_count <= debug_baseband_count + 1;
-        $display("DDC_BASEBAND: i=%0d, q=%0d, count=%0d, time=%t", 
-                 baseband_i, baseband_q, debug_baseband_count, $time);
-    end
-end
+// Debug monitoring (simulation only)
+`ifdef SIMULATION
+reg [31:0] debug_adc_count = 0;
+reg [31:0] debug_baseband_count = 0;
+
+always @(posedge clk_400m) begin
+    if (adc_data_valid_i && adc_data_valid_q && debug_adc_count < 10) begin
+        debug_adc_count <= debug_adc_count + 1;
+        $display("DDC_ADC: data=%0d, count=%0d, time=%t", 
+                 adc_data, debug_adc_count, $time);
+    end
+end
+
+always @(posedge clk_100m) begin
+    if (baseband_valid_i && baseband_valid_q && debug_baseband_count < 10) begin
+        debug_baseband_count <= debug_baseband_count + 1;
+        $display("DDC_BASEBAND: i=%0d, q=%0d, count=%0d, time=%t", 
+                 baseband_i, baseband_q, debug_baseband_count, $time);
+    end
+end
+`endif
 
 
 endmodule