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Fix synthesis blockers in 9 RTL files for Vivado compatibility

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Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
This commit is contained in:
Jason
2026-03-15 14:53:35 +02:00
parent f5a3394f23
commit c871281f1e
9 changed files with 236 additions and 159 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/chirp_memory_loader_param.v
+18 -1
View File
@@ -31,45 +31,57 @@ module chirp_memory_loader_param #(
// Initialize memory
integer i;
reg [799:0] debug_msg;
initial begin
`ifdef SIMULATION
if (DEBUG) begin
$display("[MEM] Starting memory initialization for 4 long chirp segments");
end
`endif
// === LOAD LONG CHIRP - 4 SEGMENTS ===
// Segment 0 (addresses 0-1023)
$readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 1023);
$readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 1023);
`ifdef SIMULATION
if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-1023)");
`endif
// Segment 1 (addresses 1024-2047)
$readmemh(LONG_I_FILE_SEG1, long_chirp_i, 1024, 2047);
$readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 1024, 2047);
`ifdef SIMULATION
if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (1024-2047)");
`endif
// Segment 2 (addresses 2048-3071)
$readmemh(LONG_I_FILE_SEG2, long_chirp_i, 2048, 3071);
$readmemh(LONG_Q_FILE_SEG2, long_chirp_q, 2048, 3071);
`ifdef SIMULATION
if (DEBUG) $display("[MEM] Loaded long chirp segment 2 (2048-3071)");
`endif
// Segment 3 (addresses 3072-4095)
$readmemh(LONG_I_FILE_SEG3, long_chirp_i, 3072, 4095);
$readmemh(LONG_Q_FILE_SEG3, long_chirp_q, 3072, 4095);
`ifdef SIMULATION
if (DEBUG) $display("[MEM] Loaded long chirp segment 3 (3072-4095)");
`endif
// === LOAD SHORT CHIRP ===
// Load first 50 samples (0-49)
$readmemh(SHORT_I_FILE, short_chirp_i);
$readmemh(SHORT_Q_FILE, short_chirp_q);
`ifdef SIMULATION
if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
`endif
// Zero pad remaining 974 samples (50-1023)
for (i = 50; i < 1024; i = i + 1) begin
short_chirp_i[i] = 16'h0000;
short_chirp_q[i] = 16'h0000;
end
`ifdef SIMULATION
if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-1023");
// === VERIFICATION ===
@@ -87,6 +99,7 @@ initial begin
$display(" Short[49]: I=%h Q=%h", short_chirp_i[49], short_chirp_q[49]);
$display(" Short[50]: I=%h Q=%h (zero-padded)", short_chirp_i[50], short_chirp_q[50]);
end
`endif
end
// Memory access logic
@@ -105,20 +118,24 @@ always @(posedge clk or negedge reset_n) begin
ref_i <= long_chirp_i[long_addr];
ref_q <= long_chirp_q[long_addr];
`ifdef SIMULATION
if (DEBUG && $time < 100) begin
$display("[MEM @%0t] Long chirp: seg=%b, addr=%d, I=%h, Q=%h",
$time, segment_select, long_addr,
long_chirp_i[long_addr], long_chirp_q[long_addr]);
end
`endif
end else begin
// Short chirp (0-1023)
ref_i <= short_chirp_i[sample_addr];
ref_q <= short_chirp_q[sample_addr];
`ifdef SIMULATION
if (DEBUG && $time < 100) begin
$display("[MEM @%0t] Short chirp: addr=%d, I=%h, Q=%h",
$time, sample_addr, short_chirp_i[sample_addr], short_chirp_q[sample_addr]);
end
`endif
end
mem_ready <= 1'b1;
end else begin
9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+35 -25
View File
@@ -96,15 +96,19 @@ always @(posedge clk or negedge reset_n) begin
overflow_detected <= 1'b1;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
$display("CIC_SATURATION: Positive overflow at sample %0d", sample_count);
end else if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) < -(2**35)) begin
integrator[0] <= -(2**35);
overflow_detected <= 1'b1;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
$display("CIC_SATURATION: Negative overflow at sample %0d", sample_count);
saturation_event_count <= saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_SATURATION: Positive overflow at sample %0d", sample_count);
`endif
end else if (integrator[0] + $signed({{18{data_in[17]}}, data_in}) < -(2**35)) begin
integrator[0] <= -(2**35);
overflow_detected <= 1'b1;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_SATURATION: Negative overflow at sample %0d", sample_count);
`endif
end else begin
integrator[0] <= integrator[0] + $signed({{18{data_in[17]}}, data_in});
overflow_detected <= 1'b0; // Only clear immediate detection, not latched
@@ -247,16 +251,20 @@ always @(posedge clk or negedge reset_n) begin
data_out <= 131071;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
$display("CIC_OUTPUT_SAT: TRUE Positive saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
comb[STAGES-1], temp_scaled_output, temp_output, 131071);
end else if (temp_scaled_output < -131072) begin // -2^17
data_out <= -131072;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
$display("CIC_OUTPUT_SAT: TRUE Negative saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
comb[STAGES-1], temp_scaled_output, temp_output, -131072);
saturation_event_count <= saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Positive saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
comb[STAGES-1], temp_scaled_output, temp_output, 131071);
`endif
end else if (temp_scaled_output < -131072) begin // -2^17
data_out <= -131072;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Negative saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
comb[STAGES-1], temp_scaled_output, temp_output, -131072);
`endif
end else begin
// FIXED: Use the properly truncated 18-bit value
data_out <= temp_output;
@@ -280,12 +288,14 @@ always @(posedge clk or negedge reset_n) begin
end
end
// Continuous monitoring of saturation status
always @(posedge clk) begin
if (overflow_detected && sample_count < 100) begin
$display("CIC_OVERFLOW: Immediate detection at sample %0d", sample_count);
end
end
// Continuous monitoring of saturation status
`ifdef SIMULATION
always @(posedge clk) begin
if (overflow_detected && sample_count < 100) begin
$display("CIC_OVERFLOW: Immediate detection at sample %0d", sample_count);
end
end
`endif
// Clear saturation on external reset
always @(posedge reset_monitors) begin
9_Firmware/9_2_FPGA/ddc_400m.v
+38 -34
View File
@@ -338,43 +338,47 @@ assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
// ============================================================================
// Enhanced Debug and Monitoring
// ============================================================================
reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
always @(posedge clk_100m) begin
if (fir_valid_i && debug_fir_count < 20) begin
debug_fir_count <= debug_fir_count + 1;
$display("FIR_OUTPUT: fir_i=%6d, fir_q=%6d", fir_i_out, fir_q_out);
end
if (adc_data_valid_i && adc_data_valid_q && debug_bb_count < 20) begin
debug_bb_count <= debug_bb_count + 1;
$display("BASEBAND_OUT: i=%6d, q=%6d, count=%0d",
baseband_i, baseband_q, debug_bb_count);
end
end
reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
`ifdef SIMULATION
always @(posedge clk_100m) begin
if (fir_valid_i && debug_fir_count < 20) begin
debug_fir_count <= debug_fir_count + 1;
$display("FIR_OUTPUT: fir_i=%6d, fir_q=%6d", fir_i_out, fir_q_out);
end
if (adc_data_valid_i && adc_data_valid_q && debug_bb_count < 20) begin
debug_bb_count <= debug_bb_count + 1;
$display("BASEBAND_OUT: i=%6d, q=%6d, count=%0d",
baseband_i, baseband_q, debug_bb_count);
end
end
`endif
// In ddc_400m.v, add these debug signals:
// Debug monitoring
reg [31:0] debug_adc_count = 0;
reg [31:0] debug_baseband_count = 0;
always @(posedge clk_400m) begin
if (adc_data_valid_i && adc_data_valid_q && debug_adc_count < 10) begin
debug_adc_count <= debug_adc_count + 1;
$display("DDC_ADC: data=%0d, count=%0d, time=%t",
adc_data, debug_adc_count, $time);
end
end
always @(posedge clk_100m) begin
if (baseband_valid_i && baseband_valid_q && debug_baseband_count < 10) begin
debug_baseband_count <= debug_baseband_count + 1;
$display("DDC_BASEBAND: i=%0d, q=%0d, count=%0d, time=%t",
baseband_i, baseband_q, debug_baseband_count, $time);
end
end
// Debug monitoring (simulation only)
`ifdef SIMULATION
reg [31:0] debug_adc_count = 0;
reg [31:0] debug_baseband_count = 0;
always @(posedge clk_400m) begin
if (adc_data_valid_i && adc_data_valid_q && debug_adc_count < 10) begin
debug_adc_count <= debug_adc_count + 1;
$display("DDC_ADC: data=%0d, count=%0d, time=%t",
adc_data, debug_adc_count, $time);
end
end
always @(posedge clk_100m) begin
if (baseband_valid_i && baseband_valid_q && debug_baseband_count < 10) begin
debug_baseband_count <= debug_baseband_count + 1;
$display("DDC_BASEBAND: i=%0d, q=%0d, count=%0d, time=%t",
baseband_i, baseband_q, debug_baseband_count, $time);
end
end
`endif
endmodule
9_Firmware/9_2_FPGA/fft_1024_inverse.v
+2
View File
@@ -63,6 +63,7 @@ assign ifft_valid = m_axis_data_tvalid;
assign m_axis_data_tready = 1'b1;
// Debug
`ifdef SIMULATION
reg [31:0] debug_counter;
always @(posedge clk) begin
debug_counter <= debug_counter + 1;
@@ -73,6 +74,7 @@ always @(posedge clk) begin
end
end
end
`endif
// IFFT IP instance
FFT_enhanced ifft_inverse_inst ( // Same IP core, different configuration
9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
+106 -76
View File
@@ -41,7 +41,7 @@ module matched_filter_multi_segment (
// ========== FIXED PARAMETERS ==========
parameter BUFFER_SIZE = 1024;
parameter LONG_CHIRP_SAMPLES = 3000; // Still 3000 samples total
parameter SHORT_CHIRP_SAMPLES = 50; // 0.5µs @ 100MHz
parameter SHORT_CHIRP_SAMPLES = 50; // 0.5�s @ 100MHz
parameter OVERLAP_SAMPLES = 128; // Standard for 1024-pt FFT
parameter SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES; // 896 samples
parameter DEBUG = 1; // Debug output control
@@ -162,13 +162,15 @@ always @(posedge clk or negedge reset_n) begin
// Wait for chirp start from microcontroller
if (chirp_start_pulse) begin
state <= ST_COLLECT_DATA;
total_segments <= use_long_chirp ? LONG_SEGMENTS[2:0] : SHORT_SEGMENTS[2:0];
$display("[MULTI_SEG_FIXED] Starting %s chirp, segments: %d",
use_long_chirp ? "LONG" : "SHORT",
use_long_chirp ? LONG_SEGMENTS : SHORT_SEGMENTS);
$display("[MULTI_SEG_FIXED] Overlap: %d samples, Advance: %d samples",
OVERLAP_SAMPLES, SEGMENT_ADVANCE);
total_segments <= use_long_chirp ? LONG_SEGMENTS[2:0] : SHORT_SEGMENTS[2:0];
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Starting %s chirp, segments: %d",
use_long_chirp ? "LONG" : "SHORT",
use_long_chirp ? LONG_SEGMENTS : SHORT_SEGMENTS);
$display("[MULTI_SEG_FIXED] Overlap: %d samples, Advance: %d samples",
OVERLAP_SAMPLES, SEGMENT_ADVANCE);
`endif
end
end
@@ -182,12 +184,14 @@ always @(posedge clk or negedge reset_n) begin
buffer_write_ptr <= buffer_write_ptr + 1;
chirp_samples_collected <= chirp_samples_collected + 1;
// Debug: Show first few samples
if (chirp_samples_collected < 10 && buffer_write_ptr < 10) begin
$display("[MULTI_SEG_FIXED] Store[%0d]: I=%h Q=%h",
buffer_write_ptr,
ddc_i[17:2] + ddc_i[1],
ddc_q[17:2] + ddc_q[1]);
// Debug: Show first few samples
if (chirp_samples_collected < 10 && buffer_write_ptr < 10) begin
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Store[%0d]: I=%h Q=%h",
buffer_write_ptr,
ddc_i[17:2] + ddc_i[1],
ddc_q[17:2] + ddc_q[1]);
`endif
end
// Check conditions based on chirp type
@@ -200,23 +204,29 @@ always @(posedge clk or negedge reset_n) begin
buffer_has_data <= 1;
state <= ST_WAIT_REF;
segment_request <= current_segment[1:0]; // Use lower 2 bits
mem_request <= 1;
$display("[MULTI_SEG_FIXED] Segment %d ready: %d samples collected",
current_segment, chirp_samples_collected);
mem_request <= 1;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Segment %d ready: %d samples collected",
current_segment, chirp_samples_collected);
`endif
end
// Check if end of chirp reached
if (chirp_samples_collected >= LONG_CHIRP_SAMPLES - 1) begin
chirp_complete <= 1;
$display("[MULTI_SEG_FIXED] End of long chirp reached");
if (chirp_samples_collected >= LONG_CHIRP_SAMPLES - 1) begin
chirp_complete <= 1;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] End of long chirp reached");
`endif
end
end else begin
// SHORT CHIRP: Only 50 samples, then zero-pad
if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
state <= ST_ZERO_PAD;
$display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
chirp_samples_collected + 1);
if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
state <= ST_ZERO_PAD;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
chirp_samples_collected + 1);
`endif
end
end
end
@@ -234,8 +244,10 @@ always @(posedge clk or negedge reset_n) begin
buffer_write_ptr <= 0;
state <= ST_WAIT_REF;
segment_request <= 0; // Only one segment for short chirp
mem_request <= 1;
$display("[MULTI_SEG_FIXED] Zero-pad complete, buffer full");
mem_request <= 1;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Zero-pad complete, buffer full");
`endif
end
end
@@ -246,10 +258,12 @@ always @(posedge clk or negedge reset_n) begin
buffer_processing <= 1;
buffer_read_ptr <= 0;
fft_start <= 1;
state <= ST_PROCESSING;
$display("[MULTI_SEG_FIXED] Reference ready, starting processing segment %d",
current_segment);
state <= ST_PROCESSING;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Reference ready, starting processing segment %d",
current_segment);
`endif
end
end
@@ -264,12 +278,14 @@ always @(posedge clk or negedge reset_n) begin
// 2. Request corresponding reference sample
mem_request <= 1'b1;
// Debug every 100 samples
if (buffer_read_ptr % 100 == 0) begin
$display("[MULTI_SEG_FIXED] Processing[%0d]: ADC I=%h Q=%h",
buffer_read_ptr,
input_buffer_i[buffer_read_ptr],
input_buffer_q[buffer_read_ptr]);
// Debug every 100 samples
if (buffer_read_ptr % 100 == 0) begin
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Processing[%0d]: ADC I=%h Q=%h",
buffer_read_ptr,
input_buffer_i[buffer_read_ptr],
input_buffer_q[buffer_read_ptr]);
`endif
end
buffer_read_ptr <= buffer_read_ptr + 1;
@@ -280,19 +296,23 @@ always @(posedge clk or negedge reset_n) begin
mem_request <= 0;
buffer_processing <= 0;
buffer_has_data <= 0;
state <= ST_WAIT_FFT; // CRITICAL: Wait for FFT completion
$display("[MULTI_SEG_FIXED] Finished feeding %d samples to FFT, waiting...",
BUFFER_SIZE);
state <= ST_WAIT_FFT; // CRITICAL: Wait for FFT completion
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Finished feeding %d samples to FFT, waiting...",
BUFFER_SIZE);
`endif
end
end
ST_WAIT_FFT: begin
// Wait for the processing chain to complete (2159 cycles latency)
if (fft_pc_valid) begin
state <= ST_OUTPUT;
$display("[MULTI_SEG_FIXED] FFT processing complete for segment %d",
current_segment);
if (fft_pc_valid) begin
state <= ST_OUTPUT;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] FFT processing complete for segment %d",
current_segment);
`endif
end
end
@@ -301,19 +321,23 @@ always @(posedge clk or negedge reset_n) begin
pc_i <= fft_pc_i;
pc_q <= fft_pc_q;
pc_valid <= 1;
segment_done <= 1;
$display("[MULTI_SEG_FIXED] Output segment %d: I=%h Q=%h",
current_segment, fft_pc_i, fft_pc_q);
segment_done <= 1;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Output segment %d: I=%h Q=%h",
current_segment, fft_pc_i, fft_pc_q);
`endif
// Check if we need more segments
if (current_segment < total_segments - 1 || !chirp_complete) begin
state <= ST_NEXT_SEGMENT;
end else begin
// All segments complete
state <= ST_IDLE;
$display("[MULTI_SEG_FIXED] All %d segments complete",
total_segments);
state <= ST_IDLE;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] All %d segments complete",
total_segments);
`endif
end
end
@@ -332,20 +356,24 @@ always @(posedge clk or negedge reset_n) begin
end
// Start writing after the overlap
buffer_write_ptr <= OVERLAP_SAMPLES;
$display("[MULTI_SEG_FIXED] Overlap-save: kept %d samples, write_ptr=%d",
OVERLAP_SAMPLES, OVERLAP_SAMPLES);
buffer_write_ptr <= OVERLAP_SAMPLES;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Overlap-save: kept %d samples, write_ptr=%d",
OVERLAP_SAMPLES, OVERLAP_SAMPLES);
`endif
end else begin
// Short chirp: only one segment
buffer_write_ptr <= 0;
end
// Continue collecting or finish
if (!chirp_complete) begin
state <= ST_COLLECT_DATA;
$display("[MULTI_SEG_FIXED] Starting segment %d/%d",
current_segment + 1, total_segments);
if (!chirp_complete) begin
state <= ST_COLLECT_DATA;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Starting segment %d/%d",
current_segment + 1, total_segments);
`endif
end else begin
state <= ST_IDLE;
end
@@ -385,22 +413,24 @@ matched_filter_processing_chain m_f_p_c(
.chain_state(fft_chain_state)
);
// ========== DEBUG MONITOR ==========
reg [31:0] dbg_cycles;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
dbg_cycles <= 0;
end else begin
dbg_cycles <= dbg_cycles + 1;
// Monitor state transitions
if (dbg_cycles % 1000 == 0 && state != ST_IDLE) begin
$display("[MULTI_SEG_MONITOR @%0d] state=%0d, segment=%0d/%0d, samples=%0d",
dbg_cycles, state, current_segment, total_segments,
chirp_samples_collected);
end
end
end
// ========== DEBUG MONITOR ==========
`ifdef SIMULATION
reg [31:0] dbg_cycles;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
dbg_cycles <= 0;
end else begin
dbg_cycles <= dbg_cycles + 1;
// Monitor state transitions
if (dbg_cycles % 1000 == 0 && state != ST_IDLE) begin
$display("[MULTI_SEG_MONITOR @%0d] state=%0d, segment=%0d/%0d, samples=%0d",
dbg_cycles, state, current_segment, total_segments,
chirp_samples_collected);
end
end
end
`endif
// ========== OUTPUT CONNECTIONS ==========
assign pc_i_w = fft_pc_i;
9_Firmware/9_2_FPGA/nco_400m_enhanced.v
+3 -2
View File
@@ -109,11 +109,12 @@ always @(posedge clk_400m or negedge reset_n) begin
end
end
// Add this to ensure LUT is properly loaded:
// Debug verification of LUT initialization (simulation only)
`ifdef SIMULATION
initial begin
// Wait a small amount of time for LUT initialization
#10;
$display("NCO: Sine LUT initialized with %0d entries", 64);
end
`endif
endmodule
9_Firmware/9_2_FPGA/radar_receiver_final.v
+4
View File
@@ -371,15 +371,19 @@ always @(posedge clk or negedge reset_n) begin
// Detect frame completion
if (new_chirp_frame) begin
frame_counter <= frame_counter + 1;
`ifdef SIMULATION
$display("[TOP] Frame %0d started. Previous frame had %0d chirps",
frame_counter, chirps_in_current_frame);
`endif
chirps_in_current_frame <= 0;
end
// Monitor chirp counter pattern
if (chirp_counter != chirp_counter_prev) begin
`ifdef SIMULATION
$display("[TOP] chirp_counter: %0d ? %0d",
chirp_counter_prev, chirp_counter);
`endif
end
end
end
9_Firmware/9_2_FPGA/usb_data_interface.v
+9 -10
View File
@@ -43,17 +43,16 @@ localparam FOOTER = 8'h55;
localparam FT601_DATA_WIDTH = 32;
localparam FT601_BURST_SIZE = 512; // Max burst size in bytes
typedef enum {
IDLE,
SEND_HEADER,
SEND_RANGE_DATA,
SEND_DOPPLER_DATA,
SEND_DETECTION_DATA,
SEND_FOOTER,
WAIT_ACK
} usb_state_t;
// State definitions (Verilog-2001 compatible)
localparam [2:0] IDLE = 3'd0,
SEND_HEADER = 3'd1,
SEND_RANGE_DATA = 3'd2,
SEND_DOPPLER_DATA = 3'd3,
SEND_DETECTION_DATA = 3'd4,
SEND_FOOTER = 3'd5,
WAIT_ACK = 3'd6;
usb_state_t current_state;
reg [2:0] current_state;
reg [7:0] byte_counter;
reg [31:0] data_buffer;
reg [31:0] ft601_data_out;
9_Firmware/9_2_FPGA/usb_packet_analyzer.v
+21 -11
View File
@@ -15,7 +15,7 @@ module usb_packet_analyzer (
output reg packet_valid,
output reg [7:0] packet_type,
output reg [31:0] packet_data,
output reg [31:0] error_count
output wire [31:0] error_count
);
// Packet structure
@@ -23,17 +23,15 @@ localparam HEADER = 8'hAA;
localparam FOOTER = 8'h55;
localparam HEADER_POS = 24; // Header in bits [31:24]
// States
typedef enum {
ST_IDLE,
ST_HEADER,
ST_RANGE,
ST_DOPPLER,
ST_DETECTION,
ST_FOOTER
} state_t;
// States (Verilog-2001 compatible)
localparam [2:0] ST_IDLE = 3'd0,
ST_HEADER = 3'd1,
ST_RANGE = 3'd2,
ST_DOPPLER = 3'd3,
ST_DETECTION = 3'd4,
ST_FOOTER = 3'd5;
state_t current_state, next_state;
reg [2:0] current_state, next_state;
reg [7:0] byte_count;
reg [31:0] error_reg;
reg [31:0] packet_count;
@@ -55,8 +53,10 @@ always @(posedge clk or negedge reset_n) begin
if (usb_wr_strobe && usb_data[31:24] == HEADER) begin
current_state <= ST_HEADER;
packet_count <= packet_count + 1;
`ifdef SIMULATION
$display("[USB_ANALYZER] Packet %0d started at time %0t",
packet_count + 1, $time);
`endif
end
end
@@ -82,7 +82,9 @@ always @(posedge clk or negedge reset_n) begin
packet_data[7:0] <= usb_data[7:0];
current_state <= ST_DOPPLER;
byte_count <= 8'd0;
`ifdef SIMULATION
$display("[USB_ANALYZER] Range data: 0x%08h", packet_data);
`endif
end
end
end
@@ -96,8 +98,10 @@ always @(posedge clk or negedge reset_n) begin
packet_data[15:0] <= usb_data[31:16]; // Doppler imag
current_state <= ST_DETECTION;
byte_count <= 8'd0;
`ifdef SIMULATION
$display("[USB_ANALYZER] Doppler data: real=0x%04h, imag=0x%04h",
packet_data[31:16], packet_data[15:0]);
`endif
end
end
end
@@ -106,7 +110,9 @@ always @(posedge clk or negedge reset_n) begin
if (usb_wr_strobe) begin
packet_type <= usb_data[0];
current_state <= ST_FOOTER;
`ifdef SIMULATION
$display("[USB_ANALYZER] Detection: %b", usb_data[0]);
`endif
end
end
@@ -114,11 +120,15 @@ always @(posedge clk or negedge reset_n) begin
if (usb_wr_strobe) begin
if (usb_data[7:0] == FOOTER) begin
packet_valid <= 1'b1;
`ifdef SIMULATION
$display("[USB_ANALYZER] Packet %0d valid, footer OK", packet_count);
`endif
end else begin
error_reg <= error_reg + 1;
`ifdef SIMULATION
$error("[USB_ANALYZER] Invalid footer: expected 0x55, got 0x%02h",
usb_data[7:0]);
`endif
end
current_state <= ST_IDLE;
end