diff --git a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
index 8c0b656..2c3f999 100644
--- a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
@@ -98,20 +98,24 @@ set_input_jitter [get_clocks adc_dco_p] 0.05
 # FT2232H 60 MHz CLKOUT (Bank 35, MRCC pin C4)
 # --------------------------------------------------------------------------
 # The FT2232H provides a 60 MHz clock in 245 Synchronous FIFO mode.
-# Pin C4 is IO_L12N_T1_SRCC_35 (SRCC, not MRCC — confirmed via Vivado
-# device model: IS_CLK_CAPABLE=1, IS_MASTER=0). SRCC pins cannot drive
-# BUFG through dedicated routing, which is why the earlier build needed
-# CLOCK_DEDICATED_ROUTE=FALSE and burned ~5 ns in fabric routing.
-#
-# Fix: radar_system_top.v now instantiates BUFIO+BUFR instead of BUFG
-# for USB_MODE=1 (50T). SRCC → BUFIO → BUFR is the standard 7-series
-# path for regional clock distribution; all ft_clkout-domain logic is
-# contained in bank 35 / one clock region, so regional is sufficient.
-# The CLOCK_DEDICATED_ROUTE=FALSE override is no longer needed.
+# Pin C4 is IO_L12N_T1_MRCC_35 (N-type of MRCC pair). Vivado requires
+# CLOCK_DEDICATED_ROUTE FALSE for clock inputs on N-type MRCC pins
+# (Place 30-876). The schematic routes CLKOUT to C4; this cannot be
+# changed without a board respin. The clock still uses an IBUFG and
+# reaches the clock network — the constraint only disables the DRC check.
 set_property PACKAGE_PIN C4 [get_ports {ft_clkout}]
 set_property IOSTANDARD LVCMOS33 [get_ports {ft_clkout}]
 create_clock -name ft_clkout -period 16.667 [get_ports {ft_clkout}]
 set_input_jitter [get_clocks ft_clkout] 0.2
+# N-type MRCC pin requires dedicated route override (Place 30-876).
+# Audit F-0.4: the literal net name `ft_clkout_IBUF` exists post-synth but
+# the XDC scan happens before synthesis, when the IBUF net does not yet
+# exist — Vivado reported `No nets matched 'ft_clkout_IBUF'` + CRITICAL
+# WARNING. Use -hierarchical -filter + -quiet so the constraint matches
+# post-synth without warning during pre-synth XDC scan. The TCL duplicate
+# at scripts/50t/build_50t.tcl:119 remains as belt-and-suspenders.
+set_property -quiet CLOCK_DEDICATED_ROUTE FALSE \
+    [get_nets -quiet -hierarchical -filter {NAME =~ *ft_clkout_IBUF}]
 
 # ============================================================================
 # RESET (Active-Low)
diff --git a/9_Firmware/9_2_FPGA/radar_system_top.v b/9_Firmware/9_2_FPGA/radar_system_top.v
index 56161f4..461af0f 100644
--- a/9_Firmware/9_2_FPGA/radar_system_top.v
+++ b/9_Firmware/9_2_FPGA/radar_system_top.v
@@ -327,27 +327,10 @@ BUFG bufg_120m (
     .O(clk_120m_dac_buf)
 );
 
-// USB clock buffering:
-//   USB_MODE=0 (200T/FT601): pin is MRCC (D17) → BUFG, global clock network.
-//   USB_MODE=1 (50T/FT2232H): pin is SRCC (C4, non-MRCC) → BUFIO + BUFR for
-//     regional dedicated routing. SRCC can drive BUFIO/BUFR but not BUFG
-//     directly (the "poor placement IO→BUFG" CLOCK_DEDICATED_ROUTE=FALSE
-//     override was burning ~5 ns in fabric routing on the ft_clkout path).
-//     All ft_clkout-domain logic (FT2232H FSM, FIFO flops, toggle CDCs) is
-//     contained in bank 35 / one clock region, so regional distribution
-//     is sufficient. See UG472 §3 BUFIO/BUFR.
-generate if (USB_MODE == 1) begin : gen_ft_bufr
-    wire ft_clk_bufio;
-    BUFIO bufio_ft (.I(ft601_clk_in), .O(ft_clk_bufio));
-    BUFR #(.BUFR_DIVIDE("BYPASS"), .SIM_DEVICE("7SERIES")) bufr_ft (
-        .I(ft_clk_bufio),
-        .O(ft601_clk_buf),
-        .CE(1'b1),
-        .CLR(1'b0)
-    );
-end else begin : gen_ft_bufg
-    BUFG bufg_ft601 (.I(ft601_clk_in), .O(ft601_clk_buf));
-end endgenerate
+BUFG bufg_ft601 (
+    .I(ft601_clk_in),
+    .O(ft601_clk_buf)
+);
 `endif
 
 // Reset synchronization (clk_100m domain)
diff --git a/9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl b/9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl
index 88373f6..51a0e5e 100644
--- a/9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl
+++ b/9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl
@@ -111,10 +111,12 @@ set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
 set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
 set_property SEVERITY {Warning} [get_drc_checks PLIO-9]
 
-# FT2232H CLKOUT routing: C4 is SRCC, not MRCC. Earlier builds used
-# CLOCK_DEDICATED_ROUTE=FALSE + implicit BUFG, which forced fabric routing
-# and burned ~5 ns. radar_system_top.v now uses BUFIO+BUFR for USB_MODE=1
-# (regional distribution from SRCC) so the override is no longer required.
+# FT2232H CLKOUT on C4 (N-type MRCC) — override dedicated clock route check.
+# The schematic routes the FT2232H 60 MHz clock to the N-pin of a differential
+# MRCC pair. Vivado Place 30-876 requires this property to allow placement.
+# The clock still reaches the clock network via IBUFG — this only suppresses
+# the DRC that demands the P-type pin.
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]
 
 # ---- Run implementation steps ----
 opt_design -directive Explore