Clean gitignore after root artifact reorganization

.gitignore

@@ -2,26 +2,30 @@
 *.vvp
 *.vcd
 
-# Testbench CSV output (regenerated on each run)
-mf_chain_autocorr.csv
-rbd_mode00_ramp.csv
-rbd_mode01_peak.csv
-rbd_mode10_avg.csv
-rbd_mode10_ramp.csv
-rmc_autoscan.csv
-
 # Debug / scratch RTL (not part of the design)
 9_Firmware/9_2_FPGA/debug_*.v
 9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
 9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
 9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
 
-# Stray CSV artifacts from unit testbenches
+# Local simulation artifacts and CSV outputs
 9_Firmware/9_2_FPGA/cic_*.csv
 9_Firmware/9_2_FPGA/fir_*.csv
 9_Firmware/9_2_FPGA/nco_*.csv
 9_Firmware/9_2_FPGA/ddc_*.csv
 9_Firmware/9_2_FPGA/mf_pipeline_output.csv
+9_Firmware/9_2_FPGA/mf_chain_autocorr.csv
+9_Firmware/9_2_FPGA/rbd_mode00_ramp.csv
+9_Firmware/9_2_FPGA/rbd_mode01_peak.csv
+9_Firmware/9_2_FPGA/rbd_mode10_avg.csv
+9_Firmware/9_2_FPGA/rbd_mode10_ramp.csv
+9_Firmware/9_2_FPGA/rmc_autoscan.csv
+9_Firmware/9_2_FPGA/tb/mf_chain_autocorr.csv
+9_Firmware/9_2_FPGA/tb/rbd_mode00_ramp.csv
+9_Firmware/9_2_FPGA/tb/rbd_mode01_peak.csv
+9_Firmware/9_2_FPGA/tb/rbd_mode10_avg.csv
+9_Firmware/9_2_FPGA/tb/rbd_mode10_ramp.csv
+9_Firmware/9_2_FPGA/tb/rmc_autoscan.csv
 9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
 
 # Co-sim intermediate CSVs (regenerated by scripts)
@@ -49,11 +53,4 @@ __pycache__/
 9_Firmware/9_2_FPGA/synth_only.xdc
 
 # Local timing closure report snapshots
-build6_reports/
+build*_reports/
-build7_reports/
-build8_reports/
-build9_reports/
-build10_reports/
-build11_reports/
-build12_reports/
-build13_reports/