Add new testbenches and fix USB clock forwarding test

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New testbenches:
- tb_latency_buffer.v: 13/13 tests for BRAM delay line (P1-3)
- tb_cdc_modules.v: 27/27 tests for all 3 CDC primitives (P1-4)
- tb_ad9484_xsim.v: XSim testbench for AD9484 with Xilinx BUFIO/IDDR
- tb_nco_xsim.v: XSim testbench for NCO DSP48E1 path verification

Fixes:
- tb_usb_data_interface.v: updated test 33 from divide-by-2 check to
  ODDR-style clock forwarding verification (39/39 pass)
- rx_final_doppler_out.csv: updated golden reference after bug fixes

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This commit is contained in:

Jason

2026-03-16 22:24:34 +02:00

parent 1acedf494c

commit b823d83feb

6 changed files with 3725 additions and 2062 deletions

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9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv

+2048 -2048

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