test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep
A new SCENARIO_FUZZ branch in tb_ddc_cosim.v accepts +hex / +csv / +tag plusargs so an external runner can pick stimulus and output paths per iteration. The three path registers are widened to 4 kbit each so long temp-directory paths (e.g. /private/var/folders/...) do not overflow the MSB and emerge truncated — a real failure mode caught while writing this runner. test_ddc_cosim_fuzz.py is a pytest-driven fuzz harness: - Generates a random plausible radar scene per seed (1-4 targets with random range/velocity/RCS/phase, random noise level 0.5-6.0 LSB stddev) via radar_scene.generate_adc_samples, fully deterministic. - Compiles tb_ddc_cosim.v once per session (module-scope fixture), then runs vvp per seed. - Asserts sample-count bounds consistent with 4x CIC decimation, signed-18 range on every baseband I/Q word, and non-zero output (catches silent pipeline stalls). - Ships with two tiers: test_ddc_fuzz_fast (8 seeds, default CI) and test_ddc_fuzz_full (100 seeds, opt-in via -m slow) matching the audit ask. Registers the "slow" marker in pyproject.toml for the 100-seed opt-in.
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Jason
@@ -64,9 +64,11 @@ module tb_ddc_cosim;
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// Scenario selector (set via +define)
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reg [255:0] scenario_name;
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reg [1023:0] hex_file_path;
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reg [1023:0] csv_out_path;
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reg [1023:0] csv_cic_path;
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// Widened to 4 kbits (512 bytes) so fuzz-runner temp paths
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// (e.g. /private/var/folders/.../pytest-of-...) fit without MSB truncation.
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reg [4095:0] hex_file_path;
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reg [4095:0] csv_out_path;
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reg [4095:0] csv_cic_path;
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// ── Clock generation ──────────────────────────────────────
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// 400 MHz clock
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@@ -152,7 +154,16 @@ module tb_ddc_cosim;
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// ── Select scenario ───────────────────────────────────
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// Default to DC scenario for fastest validation
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// Override with: +define+SCENARIO_SINGLE, +define+SCENARIO_MULTI, etc.
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`ifdef SCENARIO_SINGLE
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`ifdef SCENARIO_FUZZ
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// Audit F-3.2: fuzz runner provides +hex and +csv paths plus a
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// scenario tag. Any missing plusarg falls back to the DC vector.
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if (!$value$plusargs("hex=%s", hex_file_path))
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hex_file_path = "tb/cosim/adc_dc.hex";
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if (!$value$plusargs("csv=%s", csv_out_path))
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csv_out_path = "tb/cosim/rtl_bb_fuzz.csv";
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if (!$value$plusargs("tag=%s", scenario_name))
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scenario_name = "fuzz";
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`elsif SCENARIO_SINGLE
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hex_file_path = "tb/cosim/adc_single_target.hex";
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csv_out_path = "tb/cosim/rtl_bb_single_target.csv";
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scenario_name = "single_target";
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@@ -0,0 +1,185 @@
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"""
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DDC Cosim Fuzz Runner (audit F-3.2)
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===================================
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Parameterized seed sweep over the existing DDC cosim testbench.
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For each seed the runner:
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1. Generates a random plausible radar scene (1-4 targets, random range /
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velocity / RCS, random noise level) via tb/cosim/radar_scene.py, using
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the seed for full determinism.
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2. Writes a temporary ADC hex file.
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3. Compiles tb_ddc_cosim.v with -DSCENARIO_FUZZ (once, cached across seeds)
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and runs vvp with +hex, +csv, +tag plusargs.
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4. Parses the RTL output CSV and checks:
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- non-empty output (the pipeline produced baseband samples)
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- all I/Q values are within signed-18-bit range
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- no NaN / parse errors
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- sample count is within the expected bound from CIC decimation ratio
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The intent is liveness / crash-fuzz, not bit-exact cross-check. Bit-exact
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validation is covered by the static scenarios (single_target, multi_target,
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etc) in the existing suite. Fuzz complements that by surfacing edge-case
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corruption, saturation, or overflow on random-but-valid inputs.
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Marks:
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- The default fuzz sweep uses 8 seeds for fast CI.
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- Use `-m slow` to unlock the full 100-seed sweep matched to the audit ask.
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Compile + run times per seed on a laptop with iverilog 13: ~6 s. The default
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8-seed sweep fits in a ~1 minute pytest run; the 100-seed sweep takes ~10-12
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minutes.
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"""
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from __future__ import annotations
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import os
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import random
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import subprocess
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import sys
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import tempfile
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from pathlib import Path
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import pytest
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THIS_DIR = Path(__file__).resolve().parent
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REPO_ROOT = THIS_DIR.parent.parent.parent
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FPGA_DIR = REPO_ROOT / "9_Firmware" / "9_2_FPGA"
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COSIM_DIR = FPGA_DIR / "tb" / "cosim"
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sys.path.insert(0, str(COSIM_DIR))
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import radar_scene # noqa: E402
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FAST_SEEDS = list(range(8))
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SLOW_SEEDS = list(range(100))
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# Pipeline constants
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N_ADC_SAMPLES = 16384
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CIC_DECIMATION = 4
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FIR_DECIMATION = 1
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EXPECTED_BB_MIN = N_ADC_SAMPLES // (CIC_DECIMATION * 4) # pessimistic lower bound
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EXPECTED_BB_MAX = N_ADC_SAMPLES // CIC_DECIMATION # upper bound before FIR drain
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SIGNED_18_MIN = -(1 << 17)
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SIGNED_18_MAX = (1 << 17) - 1
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SOURCE_FILES = [
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"tb/tb_ddc_cosim.v",
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"ddc_400m.v",
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"nco_400m_enhanced.v",
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"cic_decimator_4x_enhanced.v",
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"fir_lowpass.v",
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"cdc_modules.v",
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]
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@pytest.fixture(scope="module")
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def compiled_fuzz_vvp(tmp_path_factory):
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"""Compile tb_ddc_cosim.v once per pytest session with SCENARIO_FUZZ."""
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iverilog = _iverilog_bin()
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if not iverilog:
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pytest.skip("iverilog not available on PATH")
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out_dir = tmp_path_factory.mktemp("ddc_fuzz_build")
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vvp = out_dir / "tb_ddc_cosim_fuzz.vvp"
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sources = [str(FPGA_DIR / p) for p in SOURCE_FILES]
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cmd = [
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iverilog, "-g2001", "-DSIMULATION", "-DSCENARIO_FUZZ",
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"-o", str(vvp), *sources,
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]
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res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False)
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if res.returncode != 0:
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pytest.skip(f"iverilog compile failed:\n{res.stderr}")
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return vvp
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def _iverilog_bin() -> str | None:
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from shutil import which
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return which("iverilog")
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def _random_scene(seed: int) -> list[radar_scene.Target]:
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rng = random.Random(seed)
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n = rng.randint(1, 4)
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return [
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radar_scene.Target(
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range_m=rng.uniform(50, 1500),
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velocity_mps=rng.uniform(-40, 40),
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rcs_dbsm=rng.uniform(-10, 20),
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phase_deg=rng.uniform(0, 360),
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)
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for _ in range(n)
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]
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def _run_seed(seed: int, vvp: Path, work: Path) -> tuple[int, list[tuple[int, int]]]:
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"""Generate stimulus, run the DUT, return (bb_sample_count, [(i,q)...])."""
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targets = _random_scene(seed)
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noise = random.Random(seed ^ 0xA5A5).uniform(0.5, 6.0)
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adc = radar_scene.generate_adc_samples(
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targets, N_ADC_SAMPLES, noise_stddev=noise, seed=seed
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)
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hex_path = work / f"adc_fuzz_{seed:04d}.hex"
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csv_path = work / f"rtl_bb_fuzz_{seed:04d}.csv"
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radar_scene.write_hex_file(str(hex_path), adc, bits=8)
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vvp_bin = _vvp_bin()
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if not vvp_bin:
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pytest.skip("vvp not available")
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cmd = [
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vvp_bin, str(vvp),
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f"+hex={hex_path}",
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f"+csv={csv_path}",
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f"+tag=seed{seed:04d}",
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]
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res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False, timeout=120)
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assert res.returncode == 0, f"vvp exit={res.returncode}\nstdout:\n{res.stdout}\nstderr:\n{res.stderr}"
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assert csv_path.exists(), (
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f"vvp completed rc=0 but CSV was not produced at {csv_path}\n"
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f"cmd: {cmd}\nstdout:\n{res.stdout[-2000:]}\nstderr:\n{res.stderr[-500:]}"
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)
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rows = []
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with csv_path.open() as fh:
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header = fh.readline()
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assert "baseband_i" in header and "baseband_q" in header, f"unexpected CSV header: {header!r}"
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for line in fh:
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parts = line.strip().split(",")
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if len(parts) != 3:
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continue
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_, i_str, q_str = parts
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rows.append((int(i_str), int(q_str)))
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return len(rows), rows
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def _vvp_bin() -> str | None:
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from shutil import which
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return which("vvp")
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def _fuzz_assertions(seed: int, rows: list[tuple[int, int]]) -> None:
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n = len(rows)
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assert EXPECTED_BB_MIN <= n <= EXPECTED_BB_MAX, (
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f"seed {seed}: bb sample count {n} outside [{EXPECTED_BB_MIN},{EXPECTED_BB_MAX}]"
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)
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for idx, (i, q) in enumerate(rows):
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assert SIGNED_18_MIN <= i <= SIGNED_18_MAX, (
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f"seed {seed} row {idx}: baseband_i={i} out of signed-18 range"
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)
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assert SIGNED_18_MIN <= q <= SIGNED_18_MAX, (
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f"seed {seed} row {idx}: baseband_q={q} out of signed-18 range"
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)
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all_zero = all(i == 0 and q == 0 for i, q in rows)
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assert not all_zero, f"seed {seed}: all-zero baseband output — pipeline likely stalled"
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@pytest.mark.parametrize("seed", FAST_SEEDS)
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def test_ddc_fuzz_fast(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
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_, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
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_fuzz_assertions(seed, rows)
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@pytest.mark.slow
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@pytest.mark.parametrize("seed", SLOW_SEEDS)
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def test_ddc_fuzz_full(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
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_, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
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_fuzz_assertions(seed, rows)
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@@ -19,6 +19,11 @@ dev = [
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# ---------------------------------------------------------------------------
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# Ruff configuration
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# ---------------------------------------------------------------------------
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[tool.pytest.ini_options]
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markers = [
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"slow: full-sweep tests (opt-in via -m slow); audit F-3.2 100-seed fuzz",
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]
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[tool.ruff]
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target-version = "py312"
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line-length = 100
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