Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
Bug: rounding logic 'adc_i <= ddc_i[17:2] + ddc_i[1]' overflows when ddc_i[17:2]=0x7FFF and ddc_i[1]=1, causing 0x7FFF+1=0x8000 (sign flip from max positive to most negative value). Fix: add explicit saturation — clamp to 0x7FFF when truncated value is max positive and round bit is set. Negative values cannot overflow since rounding only moves toward zero. New testbench: tb_ddc_input_interface.v with 26 tests covering rounding, truncation, overflow saturation at positive boundary, negative full scale, valid synchronization, and sync error detection.
This commit is contained in:
Jason
@@ -39,13 +39,25 @@ always @(posedge clk or negedge reset_n) begin
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end
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end
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// Scale 18-bit to 16-bit with rounding
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// Option: Keep most significant 16 bits with rounding
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// Scale 18-bit to 16-bit with convergent rounding + saturation
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// ddc_i[17:2] extracts the upper 16 bits; ddc_i[1] is the rounding bit.
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// Without saturation, 0x7FFF + 1 = 0x8000 (sign flip at positive full scale).
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// Fix: saturate to 0x7FFF when rounding would overflow a positive value.
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// Negative values cannot overflow: the most negative 18-bit value (-131072)
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// truncates to -8192 (0x8000 as 16-bit) and rounding only moves toward zero.
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wire [15:0] trunc_i = ddc_i[17:2];
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wire [15:0] trunc_q = ddc_q[17:2];
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wire round_i = ddc_i[1];
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wire round_q = ddc_q[1];
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// Overflow occurs only when truncated value is max positive AND round bit set
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wire sat_i = (trunc_i == 16'h7FFF) & round_i;
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wire sat_q = (trunc_q == 16'h7FFF) & round_q;
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always @(posedge clk) begin
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if (valid_sync) begin
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// Round to nearest: add 0.5 LSB before truncation
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adc_i <= ddc_i[17:2] + ddc_i[1]; // Rounding
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adc_q <= ddc_q[17:2] + ddc_q[1]; // Rounding
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adc_i <= sat_i ? 16'sh7FFF : (trunc_i + {15'b0, round_i});
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adc_q <= sat_q ? 16'sh7FFF : (trunc_q + {15'b0, round_q});
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end
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end
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@@ -0,0 +1,373 @@
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`timescale 1ns / 1ps
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/**
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* tb_ddc_input_interface.v
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*
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* Testbench for ddc_input_interface.v — 18-bit to 16-bit rounding + saturation.
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*
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* Tests:
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* 1. Reset state (outputs zero, adc_valid deasserted)
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* 2. Basic passthrough (small positive/negative values)
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* 3. Rounding up (bit[1]=1 adds 1 to truncated value)
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* 4. Rounding down (bit[1]=0, truncation only)
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* 5. Positive overflow saturation (0x1FFFC..0x1FFFF -> 0x7FFF, not 0x8000)
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* 6. Negative full scale (no overflow on negative side)
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* 7. Valid synchronization (both I and Q must be valid)
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* 8. Sync error detection (I valid without Q, and vice versa)
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* 9. Pipeline latency (2 cycles: valid_sync then adc_valid)
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* 10. Sweep from near-max-positive through overflow boundary
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*
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* Compile:
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* iverilog -g2001 -DSIMULATION -o tb/tb_ddc_input_interface.vvp \
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* tb/tb_ddc_input_interface.v ddc_input_interface.v
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*
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* vvp tb/tb_ddc_input_interface.vvp
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*/
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module tb_ddc_input_interface;
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// ============================================================================
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// Parameters
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// ============================================================================
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localparam CLK_PERIOD = 10.0; // 100 MHz
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// ============================================================================
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// Clock and reset
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// ============================================================================
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reg clk;
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reg reset_n;
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initial clk = 0;
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always #(CLK_PERIOD / 2) clk = ~clk;
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// ============================================================================
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// DUT signals
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// ============================================================================
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reg signed [17:0] ddc_i;
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reg signed [17:0] ddc_q;
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reg valid_i;
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reg valid_q;
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wire signed [15:0] adc_i;
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wire signed [15:0] adc_q;
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wire adc_valid;
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wire data_sync_error;
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// ============================================================================
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// DUT instantiation
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// ============================================================================
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ddc_input_interface dut (
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.clk(clk),
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.reset_n(reset_n),
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.ddc_i(ddc_i),
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.ddc_q(ddc_q),
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.valid_i(valid_i),
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.valid_q(valid_q),
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.adc_i(adc_i),
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.adc_q(adc_q),
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.adc_valid(adc_valid),
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.data_sync_error(data_sync_error)
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);
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// ============================================================================
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// Test infrastructure
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// ============================================================================
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integer pass_count;
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integer fail_count;
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integer test_count;
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task check;
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input cond;
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input [511:0] label;
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begin
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test_count = test_count + 1;
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if (cond) begin
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$display("[PASS] %0s", label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] %0s", label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// Helper: apply one I/Q sample and wait for output.
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//
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// The DUT has a 2-stage valid pipeline + 1 cycle data capture:
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// Cycle 0: present ddc_i/q + valid_i/q = 1
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// Cycle 1: valid_i_reg/valid_q_reg capture (NBA).
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// Cycle 2: valid_sync = 1 (NBA). adc_i/q computed from ddc_i/q at posedge.
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// DATA MUST STILL BE STABLE on ddc_i/q at this edge!
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// adc_i/q result available AFTER this posedge (NBA -> next cycle).
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// Cycle 3: adc_i/q hold the result. adc_valid = 1.
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//
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// Total: 4 posedge waits from data presentation to result availability.
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task apply_sample;
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input signed [17:0] in_i;
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input signed [17:0] in_q;
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begin
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@(posedge clk);
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ddc_i <= in_i;
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ddc_q <= in_q;
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valid_i <= 1;
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valid_q <= 1;
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@(posedge clk);
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// valid can drop but data must stay stable for valid_sync cycle
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valid_i <= 0;
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valid_q <= 0;
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// ddc_i/q stay at in_i/in_q (held by regs)
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@(posedge clk);
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// valid_sync fires this edge, data sampled into adc_i/q (NBA)
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@(posedge clk);
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// adc_i/q now hold the result. adc_valid = 1.
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@(posedge clk);
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// One more edge to ensure NBA from cycle 3 is visible
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end
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endtask
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// ============================================================================
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// VCD dump
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// ============================================================================
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initial begin
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$dumpfile("tb/tb_ddc_input_interface.vcd");
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$dumpvars(0, tb_ddc_input_interface);
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end
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// ============================================================================
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// Expected value computation (matches RTL: truncate [17:2] + round [1],
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// saturate if positive overflow)
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// ============================================================================
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function signed [15:0] expected_output;
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input signed [17:0] val;
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reg [15:0] trunc;
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reg rnd;
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begin
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trunc = val[17:2];
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rnd = val[1];
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if (trunc == 16'h7FFF && rnd)
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expected_output = 16'sh7FFF; // saturate
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else
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expected_output = trunc + {15'b0, rnd};
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end
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endfunction
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// ============================================================================
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// Main test sequence
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// ============================================================================
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integer i;
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reg signed [17:0] test_val;
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reg signed [15:0] exp_i, exp_q;
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initial begin
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// ---- Init ----
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pass_count = 0;
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fail_count = 0;
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test_count = 0;
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ddc_i = 0;
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ddc_q = 0;
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valid_i = 0;
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valid_q = 0;
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reset_n = 0;
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// ---- Reset ----
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#(CLK_PERIOD * 5);
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reset_n = 1;
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#(CLK_PERIOD * 3);
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$display("============================================================");
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$display("ddc_input_interface Testbench");
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$display("18-bit to 16-bit rounding with overflow saturation");
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$display("============================================================");
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// ---- Test 1: Reset state ----
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check(adc_valid == 0, "adc_valid deasserted after reset");
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check(data_sync_error == 0, "No sync error after reset");
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// ---- Test 2: Basic passthrough — small positive ----
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// ddc_i = 18'd100 = 0x00064. [17:2] = 25, [1] = 0. Expected: 25.
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apply_sample(18'sd100, 18'sd200);
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exp_i = expected_output(18'sd100);
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exp_q = expected_output(18'sd200);
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check(adc_i == exp_i,
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"Small positive I: 100 -> expected truncated+round");
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check(adc_q == exp_q,
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"Small positive Q: 200 -> expected truncated+round");
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// ---- Test 3: Small negative ----
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apply_sample(-18'sd100, -18'sd200);
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exp_i = expected_output(-18'sd100);
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exp_q = expected_output(-18'sd200);
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check(adc_i == exp_i,
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"Small negative I: -100 -> expected truncated+round");
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check(adc_q == exp_q,
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"Small negative Q: -200 -> expected truncated+round");
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// ---- Test 4: Rounding UP (bit[1]=1 on positive value) ----
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// 18'd6 = 0b000000000000000110. [17:2]=1, [1]=1. Expected: 1+1=2.
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apply_sample(18'sd6, 18'sd6);
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check(adc_i == 16'sd2,
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"Rounding up I: 6 -> [17:2]=1, [1]=1, result=2");
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check(adc_q == 16'sd2,
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"Rounding up Q: 6 -> [17:2]=1, [1]=1, result=2");
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// ---- Test 5: Rounding DOWN (bit[1]=0) ----
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// 18'd4 = 0b000000000000000100. [17:2]=1, [1]=0. Expected: 1.
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apply_sample(18'sd4, 18'sd4);
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check(adc_i == 16'sd1,
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"Truncation (no round) I: 4 -> [17:2]=1, [1]=0, result=1");
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check(adc_q == 16'sd1,
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"Truncation (no round) Q: 4 -> [17:2]=1, [1]=0, result=1");
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// ---- Test 6: CRITICAL — Positive overflow saturation ----
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// Maximum 18-bit positive = 131071 = 18'h1FFFF
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// [17:2] = 16'h7FFF = 32767, [1] = 1
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// WITHOUT saturation: 32767 + 1 = -32768 (sign flip!)
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// WITH saturation: 32767 (clamped)
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apply_sample(18'sd131071, 18'sd131071);
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check(adc_i == 16'sh7FFF,
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"Positive overflow saturation I: 131071 -> 0x7FFF (not 0x8000)");
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check(adc_q == 16'sh7FFF,
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"Positive overflow saturation Q: 131071 -> 0x7FFF (not 0x8000)");
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// ---- Test 7: Near-overflow, no saturation needed ----
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// 18'sd131068 = 0x1FFFC. [17:2] = 0x7FFF, [1] = 0. Expected: 0x7FFF.
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apply_sample(18'sd131068, 18'sd131068);
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check(adc_i == 16'sh7FFF,
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"Near-overflow no-round I: 131068 -> 0x7FFF (no saturation needed)");
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check(adc_q == 16'sh7FFF,
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"Near-overflow no-round Q: 131068 -> 0x7FFF (no saturation needed)");
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// ---- Test 8: Just below overflow boundary ----
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// 18'sd131066 = 0x1FFFA. [17:2] = 0x7FFE, [1] = 1. Expected: 0x7FFE+1=0x7FFF.
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apply_sample(18'sd131066, 18'sd131066);
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check(adc_i == 16'sh7FFF,
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"Below overflow, round up I: 131066 -> 0x7FFF");
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check(adc_q == 16'sh7FFF,
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"Below overflow, round up Q: 131066 -> 0x7FFF");
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// ---- Test 9: Negative full scale ----
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// Minimum 18-bit signed = -131072 = 18'h20000
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// [17:2] = 0x8000 = -32768, [1] = 0. Expected: -32768.
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apply_sample(-18'sd131072, -18'sd131072);
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check(adc_i == -16'sd32768,
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"Negative full scale I: -131072 -> -32768 (0x8000)");
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check(adc_q == -16'sd32768,
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"Negative full scale Q: -131072 -> -32768 (0x8000)");
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// ---- Test 10: Negative near-min with rounding ----
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// -131071 = 18'sh20001. [17:2] = 0x8000 = -32768, [1] = 0. Expected: -32768.
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apply_sample(-18'sd131071, -18'sd131071);
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exp_i = expected_output(-18'sd131071);
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check(adc_i == exp_i,
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"Negative near-min I: -131071 -> expected");
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// ---- Test 11: Zero ----
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apply_sample(18'sd0, 18'sd0);
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check(adc_i == 16'sd0, "Zero I: 0 -> 0");
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check(adc_q == 16'sd0, "Zero Q: 0 -> 0");
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// ---- Test 12: Valid synchronization — only I valid ----
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@(posedge clk);
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ddc_i <= 18'sd999;
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ddc_q <= 18'sd999;
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valid_i <= 1;
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valid_q <= 0;
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@(posedge clk);
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// data_sync_error = valid_i_reg ^ valid_q_reg, 1 cycle after inputs
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valid_i <= 0;
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@(posedge clk);
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check(data_sync_error == 1,
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"Sync error detected: valid_i=1, valid_q=0");
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@(posedge clk);
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// ---- Test 13: Valid synchronization — only Q valid ----
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@(posedge clk);
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ddc_i <= 18'sd999;
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ddc_q <= 18'sd999;
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valid_i <= 0;
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valid_q <= 1;
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@(posedge clk);
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valid_q <= 0;
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@(posedge clk);
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check(data_sync_error == 1,
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"Sync error detected: valid_i=0, valid_q=1");
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@(posedge clk);
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// ---- Test 14: No sync error when both valid ----
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@(posedge clk);
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valid_i <= 1;
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valid_q <= 1;
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@(posedge clk);
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valid_i <= 0;
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valid_q <= 0;
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@(posedge clk);
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check(data_sync_error == 0,
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"No sync error when both valid");
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@(posedge clk);
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// ---- Test 15: Sweep near overflow boundary ----
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// Test values from 131064 to 131071 — covers all rounding/saturation cases
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begin : sweep_test
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integer sweep_pass;
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reg signed [17:0] sv;
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reg signed [15:0] exp_sv;
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sweep_pass = 1;
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for (i = 131064; i <= 131071; i = i + 1) begin
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sv = i;
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apply_sample(sv, sv);
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exp_sv = expected_output(sv);
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if (adc_i !== exp_sv) begin
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sweep_pass = 0;
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$display(" SWEEP FAIL: input=%0d, expected=%0d, got=%0d",
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i, exp_sv, adc_i);
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end
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end
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check(sweep_pass == 1,
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"Overflow boundary sweep (131064..131071) all correct");
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end
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// ---- Test 16: Sweep near negative boundary ----
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begin : neg_sweep_test
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integer neg_sweep_pass;
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reg signed [17:0] sv;
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reg signed [15:0] exp_sv;
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neg_sweep_pass = 1;
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for (i = -131072; i <= -131064; i = i + 1) begin
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sv = i;
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apply_sample(sv, sv);
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exp_sv = expected_output(sv);
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if (adc_i !== exp_sv) begin
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neg_sweep_pass = 0;
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$display(" NEG SWEEP FAIL: input=%0d, expected=%0d, got=%0d",
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i, exp_sv, adc_i);
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end
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end
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check(neg_sweep_pass == 1,
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"Negative boundary sweep (-131072..-131064) all correct");
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end
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// ---- Summary ----
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$display("\n============================================================");
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$display("RESULTS: %0d / %0d passed", pass_count, test_count);
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$display("============================================================");
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if (fail_count == 0) begin
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$display("ALL TESTS PASSED");
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end else begin
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$display("SOME TESTS FAILED");
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end
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$display("============================================================");
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#(CLK_PERIOD * 5);
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$finish;
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end
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// ============================================================================
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// Watchdog
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// ============================================================================
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initial begin
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#(CLK_PERIOD * 100_000);
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$display("WATCHDOG TIMEOUT");
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$display("SOME TESTS FAILED");
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$finish;
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end
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endmodule
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