From a31b4ec4842c5cb8bfd1006323f40861c251f3c2 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Fri, 20 Mar 2026 01:46:24 +0200 Subject: [PATCH] Update docs for FFT optimizations + E2E test + RTL fixes (19/19 FPGA regression) --- docs/implementation-log.html | 10 +++++++++- docs/release-notes.html | 12 ++++++++++++ docs/reports.html | 5 +++-- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/docs/implementation-log.html b/docs/implementation-log.html index 540ed82..7dfed3c 100644 --- a/docs/implementation-log.html +++ b/docs/implementation-log.html @@ -30,6 +30,14 @@

Recent milestone timeline

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+

E2E integration test + RTL fixes: mixer sequencing, USB data-pending, receiver wiring (0773001)

+

New end-to-end testbench (tb_system_e2e.v) with 46 checks across 12 groups covering reset, TX, safety, RX, USB R/W, CDC, beam scanning, reset recovery, stream control, latency budgets, and watchdog. RTL fixes discovered via E2E: chirp controller TX/RX mixer enables now mutually exclusive by FSM state; USB write FSM gains doppler/cfar data_pending sticky flags with stream-control reset default changed to range-only (3'b001); receiver gets STM32 toggle signal inputs and dynamic frame detection. USB unit tests 21/22/56 updated for data_pending architecture. Regression script PASS/FAIL parsing hardened. 19/19 FPGA, 20/20 MCU.

+
+
+

FFT engine optimizations: 4-cycle butterfly + barrel-shift twiddle (a3e1996)

+

Merged SHIFT state into WRITE stage for a 5→4 cycle butterfly pipeline (20% throughput improvement). Replaced multiplier-based twiddle factor index computation with variable left-shift (barrel shift), freeing one DSP48 multiplier. Both changes verified via FFT testbench.

+

Gap 2: GUI Settings — runtime chirp timing, stream control, status readback (7cdfa48)

Radar chirp timing parameters (long/short chirp, listen, guard cycles, chirps-per-elevation) are now runtime-configurable via 6 new USB opcodes (0x10-0x15). Stream control (opcode 0x04) gates the USB write FSM per-stream. CFAR threshold (opcode 0x03) is wired to actual comparison logic (was hardcoded). Status readback (opcode 0xFF) returns a 7-word packet with all current settings. CDC handled via per-bit 2-stage synchronizers (stream control) and toggle CDC (status request). 4 new testbench groups added. 18/18 FPGA, 20/20 MCU.

@@ -73,7 +81,7 @@

Codebase quality and verification upgrades

    -
  • FPGA regression: 18/18 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, and system-top integration.
    • +
  • FPGA regression: 19/19 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, system-top integration, and system E2E.
  • MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).
  • Architectural gaps 2, 3, 4, 5, 7 closed with full test coverage. Gaps 1 and 6 deferred to post-bring-up.
  • USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control. GUI settings (chirp timing, stream gating, status readback) fully operational.
    • diff --git a/docs/release-notes.html b/docs/release-notes.html index 730a938..969d1d3 100644 --- a/docs/release-notes.html +++ b/docs/release-notes.html @@ -39,6 +39,16 @@ + + 0773001 + E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring + New 46-check E2E testbench (tb_system_e2e.v) across 12 groups. RTL fixes: TX/RX mixer enables mutually exclusive by FSM state, USB write FSM data_pending sticky flags with stream-control reset default 3'b001, STM32 toggle signal wiring for mode-00, dynamic frame detection. USB tests 21/22/56 and regression script PASS/FAIL parsing fixed. 19/19 FPGA, 20/20 MCU. + + + a3e1996 + FFT engine: merge SHIFT into WRITE (4-cycle butterfly) + barrel-shift twiddle index + SHIFT state merged into WRITE for 5→4 cycle butterfly (20% throughput gain). Multiplier-based twiddle index replaced with barrel-shift (frees 1 DSP48). Verified via FFT testbench; no timing regression expected. + 7cdfa48 Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback @@ -130,6 +140,8 @@

    Open in GitHub

      +
    • 0773001 E2E test + RTL fixes
      • +
    • a3e1996 FFT engine optimizations
    • 7cdfa48 Gap 2 GUI Settings
    • e5d1b3c Gap 4 USB Read Path
    • c6103b3 Gap 7 MMCM + CREG (v0.1.3-build20)
      • diff --git a/docs/reports.html b/docs/reports.html index bf09d24..f3fd638 100644 --- a/docs/reports.html +++ b/docs/reports.html @@ -57,7 +57,7 @@ Production-target XDC9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdcConstraint source of truth for the production FPGA targetTracked and validated after Build 16 cleanup port FPGA programming flow9_Firmware/9_2_FPGA/scripts/program_fpga.tclPrograms the device and reports DONE / INIT_COMPLETE / probes presencePrimary operator-facing programming script Debug probe insertion flow9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tclUsed when generating or refreshing debug-capable imagesKeep matched with the selected debug bitstream - FPGA regression runner9_Firmware/9_2_FPGA/run_regression.shPre-arrival regression evidence for the tracked FPGA baseline18 / 18 passing on the current tracked branch + FPGA regression runner9_Firmware/9_2_FPGA/run_regression.shPre-arrival regression evidence for the tracked FPGA baseline19 / 19 passing on the current tracked branch (includes E2E test) MCU regression harness9_Firmware/9_1_Microcontroller/tests/MakefilePre-arrival firmware regression evidence before flashing hardware20 / 20 passing on the current tracked branch Bring-up logging macros9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.hDefines the main first-power-on log vocabulary used over USART3Observation-only instrumentation layer Board-day worksheetdocs/board-day-worksheet.htmlRecord pass/fail, measurements, and blockers during first sessionsUse with this page and the bring-up plan @@ -113,7 +113,8 @@
      • The current routed production-target baseline is Build 20 (v0.1.3-build20) with all timing constraints met and 7x setup slack improvement over Build 18.
      • Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.
        • -
      • FPGA regression: 18/18 pass. MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).
        • +
      • FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).
        • +
      • FFT engine optimized: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (frees 1 DSP48). Pending Vivado build verification.
      • Detailed Build 20 engineering reports are on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build20/.
      • The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.