feat(rtl): add radar_system_top_50t wrapper to solve IO pin overflow
The XC7A50T-FTG256 has only 69 usable IO pins but radar_system_top declares 182 port bits. Previous attempts to remove unconstrained ports via TCL caused opt_design to cascade-remove all driving logic. New approach: radar_system_top_50t.v is a thin wrapper that: - Exposes only the 64 physically-connected ports (ADC, DAC, SPI, clocks) - Instantiates radar_system_top internally with full logic preserved - Ties off unused inputs (FT601 bus, ext trigger) to safe defaults - Leaves unused outputs internally connected (no IOBs created) Updated build_50t_test.tcl to use radar_system_top_50t as top module and removed the now-unnecessary port removal TCL code.
This commit is contained in:
Jason
@@ -0,0 +1,187 @@
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`timescale 1ns / 1ps
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/**
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* radar_system_top_50t.v
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*
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* 50T Production Wrapper for radar_system_top
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*
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* The XC7A50T-FTG256 has only 69 usable IO pins, but radar_system_top
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* declares 182 port bits (including FT601 USB 3.0, debug outputs, and
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* status signals that have no physical connections on the 50T board).
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*
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* This wrapper exposes only the 64 physically-connected ports and ties
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* off unused inputs. Unused outputs remain internally connected so the
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* full radar pipeline is preserved in the netlist.
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*/
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module radar_system_top_50t (
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// ===== System Clocks (Bank 15: 3.3V) =====
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input wire clk_100m,
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input wire clk_120m_dac,
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input wire reset_n,
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// ===== DAC Interface (Bank 15: 3.3V) =====
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output wire [7:0] dac_data,
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output wire dac_sleep,
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// ===== RF Control (Bank 15: 3.3V) =====
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output wire fpga_rf_switch,
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output wire rx_mixer_en,
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output wire tx_mixer_en,
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// ===== ADAR1000 Beamformer (Bank 34: 1.8V) =====
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output wire adar_tx_load_1, adar_rx_load_1,
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output wire adar_tx_load_2, adar_rx_load_2,
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output wire adar_tx_load_3, adar_rx_load_3,
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output wire adar_tx_load_4, adar_rx_load_4,
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output wire adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4,
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// ===== STM32 SPI 3.3V side (Bank 15) =====
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input wire stm32_sclk_3v3,
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input wire stm32_mosi_3v3,
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output wire stm32_miso_3v3,
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input wire stm32_cs_adar1_3v3, stm32_cs_adar2_3v3,
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input wire stm32_cs_adar3_3v3, stm32_cs_adar4_3v3,
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// ===== STM32 SPI 1.8V side (Bank 34) =====
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output wire stm32_sclk_1v8,
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output wire stm32_mosi_1v8,
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input wire stm32_miso_1v8,
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output wire stm32_cs_adar1_1v8, stm32_cs_adar2_1v8,
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output wire stm32_cs_adar3_1v8, stm32_cs_adar4_1v8,
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// ===== ADC Interface (Bank 14: LVDS_25) =====
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input wire [7:0] adc_d_p,
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input wire [7:0] adc_d_n,
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input wire adc_dco_p,
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input wire adc_dco_n,
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output wire adc_pwdn,
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// ===== STM32 Control (Bank 15: 3.3V) =====
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input wire stm32_new_chirp,
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input wire stm32_new_elevation,
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input wire stm32_new_azimuth,
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input wire stm32_mixers_enable
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);
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// ===== Tie-off wires for unconstrained inputs =====
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wire ft601_clk_in_tied = 1'b0;
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wire ft601_txe_tied = 1'b0;
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wire ft601_rxf_tied = 1'b0;
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wire [1:0] ft601_srb_tied = 2'b00;
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wire [1:0] ft601_swb_tied = 2'b00;
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// ===== FT601 inout bus — tie to high-Z =====
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wire [31:0] ft601_data_internal;
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assign ft601_data_internal = 32'hZZZZZZZZ;
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// ===== Unconnected output wires (synthesis preserves driving logic) =====
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wire dac_clk_nc;
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wire [3:0] ft601_be_nc;
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wire ft601_txe_n_nc;
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wire ft601_rxf_n_nc;
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wire ft601_wr_n_nc;
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wire ft601_rd_n_nc;
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wire ft601_oe_n_nc;
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wire ft601_siwu_n_nc;
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wire ft601_clk_out_nc;
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wire [5:0] current_elevation_nc;
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wire [5:0] current_azimuth_nc;
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wire [5:0] current_chirp_nc;
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wire new_chirp_frame_nc;
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wire [31:0] dbg_doppler_data_nc;
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wire dbg_doppler_valid_nc;
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wire [4:0] dbg_doppler_bin_nc;
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wire [5:0] dbg_range_bin_nc;
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wire [3:0] system_status_nc;
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radar_system_top u_core (
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// ----- Clocks & Reset -----
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.clk_100m (clk_100m),
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.clk_120m_dac (clk_120m_dac),
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.ft601_clk_in (ft601_clk_in_tied),
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.reset_n (reset_n),
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// ----- DAC -----
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.dac_data (dac_data),
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.dac_clk (dac_clk_nc),
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.dac_sleep (dac_sleep),
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// ----- RF -----
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.fpga_rf_switch (fpga_rf_switch),
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.rx_mixer_en (rx_mixer_en),
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.tx_mixer_en (tx_mixer_en),
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// ----- Beamformer -----
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.adar_tx_load_1 (adar_tx_load_1),
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.adar_rx_load_1 (adar_rx_load_1),
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.adar_tx_load_2 (adar_tx_load_2),
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.adar_rx_load_2 (adar_rx_load_2),
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.adar_tx_load_3 (adar_tx_load_3),
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.adar_rx_load_3 (adar_rx_load_3),
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.adar_tx_load_4 (adar_tx_load_4),
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.adar_rx_load_4 (adar_rx_load_4),
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.adar_tr_1 (adar_tr_1),
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.adar_tr_2 (adar_tr_2),
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.adar_tr_3 (adar_tr_3),
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.adar_tr_4 (adar_tr_4),
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// ----- SPI 3.3V -----
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.stm32_sclk_3v3 (stm32_sclk_3v3),
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.stm32_mosi_3v3 (stm32_mosi_3v3),
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.stm32_miso_3v3 (stm32_miso_3v3),
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.stm32_cs_adar1_3v3 (stm32_cs_adar1_3v3),
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.stm32_cs_adar2_3v3 (stm32_cs_adar2_3v3),
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.stm32_cs_adar3_3v3 (stm32_cs_adar3_3v3),
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.stm32_cs_adar4_3v3 (stm32_cs_adar4_3v3),
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// ----- SPI 1.8V -----
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.stm32_sclk_1v8 (stm32_sclk_1v8),
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.stm32_mosi_1v8 (stm32_mosi_1v8),
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.stm32_miso_1v8 (stm32_miso_1v8),
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.stm32_cs_adar1_1v8 (stm32_cs_adar1_1v8),
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.stm32_cs_adar2_1v8 (stm32_cs_adar2_1v8),
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.stm32_cs_adar3_1v8 (stm32_cs_adar3_1v8),
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.stm32_cs_adar4_1v8 (stm32_cs_adar4_1v8),
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// ----- ADC -----
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.adc_d_p (adc_d_p),
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.adc_d_n (adc_d_n),
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.adc_dco_p (adc_dco_p),
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.adc_dco_n (adc_dco_n),
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.adc_pwdn (adc_pwdn),
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// ----- STM32 Control -----
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.stm32_new_chirp (stm32_new_chirp),
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.stm32_new_elevation (stm32_new_elevation),
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.stm32_new_azimuth (stm32_new_azimuth),
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.stm32_mixers_enable (stm32_mixers_enable),
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// ----- FT601 (unwired on 50T) -----
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.ft601_data (ft601_data_internal),
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.ft601_be (ft601_be_nc),
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.ft601_txe_n (ft601_txe_n_nc),
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.ft601_rxf_n (ft601_rxf_n_nc),
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.ft601_txe (ft601_txe_tied),
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.ft601_rxf (ft601_rxf_tied),
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.ft601_wr_n (ft601_wr_n_nc),
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.ft601_rd_n (ft601_rd_n_nc),
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.ft601_oe_n (ft601_oe_n_nc),
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.ft601_siwu_n (ft601_siwu_n_nc),
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.ft601_srb (ft601_srb_tied),
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.ft601_swb (ft601_swb_tied),
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.ft601_clk_out (ft601_clk_out_nc),
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// ----- Status/Debug (no pins on 50T) -----
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.current_elevation (current_elevation_nc),
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.current_azimuth (current_azimuth_nc),
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.current_chirp (current_chirp_nc),
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.new_chirp_frame (new_chirp_frame_nc),
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.dbg_doppler_data (dbg_doppler_data_nc),
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.dbg_doppler_valid (dbg_doppler_valid_nc),
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.dbg_doppler_bin (dbg_doppler_bin_nc),
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.dbg_range_bin (dbg_range_bin_nc),
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.system_status (system_status_nc)
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);
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endmodule
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@@ -9,7 +9,7 @@ set project_root [file normalize [file join $script_dir ".."]]
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set project_dir [file join $project_root "build_50t"]
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set rtl_dir $project_root
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set fpga_part "xc7a50tftg256-2"
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set top_module "radar_system_top"
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set top_module "radar_system_top_50t"
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puts "================================================================"
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puts " AERIS-10 — XC7A50T Production Build"
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@@ -51,7 +51,12 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
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# NOTE: DRC severity waivers are set both before synthesis and after open_run
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# synth_1. Implementation uses direct commands (opt_design, place_design, etc.)
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# rather than launch_runs/wait_on_run, so all commands share the same Vivado
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# context. This also allows removing unconstrained ports before placement.
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# context where the waivers are active.
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#
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# The top module is radar_system_top_50t — a thin wrapper that exposes only
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# the 64 physically-connected ports on the FTG256 board. Unconstrained ports
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# (FT601, debug, status) are tied off internally, keeping the full radar
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# pipeline intact while fitting within the 69 available IO pins.
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#
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# BIVC-1: Bank 14 VCCO=2.5V (enforced by LVDS_25) with LVCMOS25 adc_pwdn.
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# This should no longer fire now that adc_pwdn is LVCMOS25, but we keep
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@@ -86,8 +91,8 @@ report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
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# ===== IMPLEMENTATION (non-project-mode style) =====
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# We run implementation steps directly in the parent process instead of
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# using launch_runs/wait_on_run. This ensures DRC waivers and port removal
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# commands execute in the same Vivado context as place_design.
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# using launch_runs/wait_on_run. This ensures DRC waivers are active in
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# the same Vivado context as place_design.
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set impl_start [clock seconds]
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# Re-apply DRC waivers in this context (parent process)
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@@ -95,43 +100,6 @@ set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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# ---- Remove unconstrained ports from netlist ----
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# The 50T board (FTG256, 69 usable IOs) cannot accommodate all 182 port bits.
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# These ports have no physical connections on the 50T PCB: FT601 USB 3.0
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# (chip unwired), dac_clk (driven by AD9523, not FPGA), and all
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# status/debug outputs. Removing them from the netlist avoids [Place 30-58].
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set unconstrained_ports {
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ft601_clk_in ft601_data ft601_be ft601_txe_n ft601_rxf_n
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ft601_txe ft601_rxf ft601_wr_n ft601_rd_n ft601_oe_n
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ft601_siwu_n ft601_srb ft601_swb ft601_clk_out
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dac_clk
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current_elevation current_azimuth current_chirp new_chirp_frame
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dbg_doppler_data dbg_doppler_valid dbg_doppler_bin dbg_range_bin
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system_status
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}
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set removed_count 0
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foreach p $unconstrained_ports {
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# Match scalar port or bus port bits (e.g., "ft601_data" matches ft601_data[*])
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set port_objs [get_ports -quiet "${p}\[*\]"]
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if {[llength $port_objs] == 0} {
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set port_objs [get_ports -quiet $p]
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}
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foreach port_obj $port_objs {
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# Disconnect the net(s) driving/driven by this port first
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set net_objs [get_nets -quiet -of_objects $port_obj]
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foreach net_obj $net_objs {
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catch {disconnect_net -net $net_obj -objects $port_obj}
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}
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# Now remove the disconnected port
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if {[catch {remove_port $port_obj} err]} {
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puts " WARN: Could not remove port $port_obj: $err"
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} else {
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incr removed_count
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}
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}
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}
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puts " Removed $removed_count unconstrained port(s) from netlist"
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# ---- Run implementation steps ----
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opt_design -directive Explore
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place_design -directive Explore
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