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module usb_data_interface (
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input wire clk, // Main clock (100MHz recommended)
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input wire reset_n,
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// Radar data inputs
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input wire [31:0] range_profile,
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input wire range_valid,
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input wire [15:0] doppler_real,
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input wire [15:0] doppler_imag,
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input wire doppler_valid,
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input wire cfar_detection,
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input wire cfar_valid,
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// FT601 Interface (Slave FIFO mode)
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// Data bus
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inout wire [31:0] ft601_data, // 32-bit bidirectional data bus
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output reg [1:0] ft601_be, // Byte enable (for 32-bit mode)
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// Control signals
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output reg ft601_txe_n, // Transmit enable (active low)
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output reg ft601_rxf_n, // Receive enable (active low)
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input wire ft601_txe, // Transmit FIFO empty
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input wire ft601_rxf, // Receive FIFO full
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output reg ft601_wr_n, // Write strobe (active low)
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output reg ft601_rd_n, // Read strobe (active low)
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output reg ft601_oe_n, // Output enable (active low)
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output reg ft601_siwu_n, // Send immediate / Wakeup
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// FIFO flags
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input wire [1:0] ft601_srb, // Selected read buffer
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input wire [1:0] ft601_swb, // Selected write buffer
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// Clock
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output reg ft601_clk_out, // Output clock to FT601 (optional)
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input wire ft601_clk_in // Clock from FT601 (60/100MHz)
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);
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// USB packet structure (same as before)
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localparam HEADER = 8'hAA;
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localparam FOOTER = 8'h55;
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// FT601 configuration
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localparam FT601_DATA_WIDTH = 32;
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localparam FT601_BURST_SIZE = 512; // Max burst size in bytes
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typedef enum {
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IDLE,
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SEND_HEADER,
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SEND_RANGE_DATA,
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SEND_DOPPLER_DATA,
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SEND_DETECTION_DATA,
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SEND_FOOTER,
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WAIT_ACK
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} usb_state_t;
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usb_state_t current_state;
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reg [7:0] byte_counter;
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reg [31:0] data_buffer;
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reg [31:0] ft601_data_out;
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reg ft601_data_oe; // Output enable for bidirectional data bus
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// FT601 data bus direction control
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assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
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always @(posedge ft601_clk_in or negedge reset_n) begin
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if (!reset_n) begin
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current_state <= IDLE;
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byte_counter <= 0;
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ft601_data_out <= 0;
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ft601_data_oe <= 0;
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ft601_be <= 2'b11; // Both bytes enabled for 32-bit mode
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ft601_txe_n <= 1;
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ft601_rxf_n <= 1;
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ft601_wr_n <= 1;
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ft601_rd_n <= 1;
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ft601_oe_n <= 1;
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ft601_siwu_n <= 1;
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ft601_clk_out <= 0;
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end else begin
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case (current_state)
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IDLE: begin
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ft601_wr_n <= 1;
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ft601_data_oe <= 0; // Release data bus
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if (range_valid || doppler_valid || cfar_valid) begin
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current_state <= SEND_HEADER;
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byte_counter <= 0;
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end
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end
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SEND_HEADER: begin
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if (!ft601_txe) begin // FT601 TX FIFO not empty
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ft601_data_oe <= 1;
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ft601_data_out <= {24'b0, HEADER};
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ft601_be <= 2'b01; // Only lower byte valid
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ft601_wr_n <= 0; // Assert write strobe
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current_state <= SEND_RANGE_DATA;
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end
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end
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SEND_RANGE_DATA: begin
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if (!ft601_txe) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b11; // All bytes valid for 32-bit word
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case (byte_counter)
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0: ft601_data_out <= range_profile;
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1: ft601_data_out <= {range_profile[23:0], 8'h00};
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2: ft601_data_out <= {range_profile[15:0], 16'h0000};
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3: ft601_data_out <= {range_profile[7:0], 24'h000000};
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endcase
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ft601_wr_n <= 0;
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if (byte_counter == 3) begin
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byte_counter <= 0;
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current_state <= SEND_DOPPLER_DATA;
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end else begin
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byte_counter <= byte_counter + 1;
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end
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end
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end
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SEND_DOPPLER_DATA: begin
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if (!ft601_txe && doppler_valid) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b11;
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case (byte_counter)
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0: ft601_data_out <= {doppler_real, doppler_imag};
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1: ft601_data_out <= {doppler_imag, doppler_real[15:8], 8'h00};
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2: ft601_data_out <= {doppler_real[7:0], doppler_imag[15:8], 16'h0000};
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3: ft601_data_out <= {doppler_imag[7:0], 24'h000000};
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endcase
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ft601_wr_n <= 0;
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if (byte_counter == 3) begin
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byte_counter <= 0;
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current_state <= SEND_DETECTION_DATA;
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end else begin
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byte_counter <= byte_counter + 1;
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end
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end
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end
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SEND_DETECTION_DATA: begin
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if (!ft601_txe && cfar_valid) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b01;
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ft601_data_out <= {24'b0, 7'b0, cfar_detection};
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ft601_wr_n <= 0;
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current_state <= SEND_FOOTER;
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end
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end
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SEND_FOOTER: begin
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if (!ft601_txe) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b01;
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ft601_data_out <= {24'b0, FOOTER};
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ft601_wr_n <= 0;
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current_state <= WAIT_ACK;
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end
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end
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WAIT_ACK: begin
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ft601_wr_n <= 1;
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ft601_data_oe <= 0; // Release data bus
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current_state <= IDLE;
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end
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endcase
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end
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end
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// Generate clock for FT601 if needed (optional)
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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ft601_clk_out <= 0;
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end else begin
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ft601_clk_out <= ~ft601_clk_out; // Divide by 2 from main clock
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end
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end
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endmodule
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