fix(fpga): harden XDC constraints + anchor ADC overflow/clock-tap pins
XDC (xc7a50t_ftg256.xdc):
- Tighten FT2232H set_input_delay -min from 0.0 -> 1.0 ns
(Tco_min + trace_min estimate; 0.0 was unrealistic and under-constrained hold).
- Tighten FT2232H set_output_delay -max from 11.667 -> 5.5 ns
(Tsu_FT ~5 ns + trace_max; previous value budgeted the full 16.67 ns period).
- Replace pairwise 'set_false_path -from CLK -to CLK' CDC waivers with
'set_clock_groups -asynchronous' for the four domain pairs:
clk_100m <-> adc_dco_p, clk_100m <-> clk_120m_dac,
clk_100m <-> ft_clkout, clk_120m_dac <-> ft_clkout.
Rationale: clock-groups is the idiomatic SDC form. Pairwise false_path is
over-broad and masks inadvertent unrelated CDCs introduced in future PRs.
Narrow register-level false_path on reset_sync_reg[*] is kept.
radar_system_top_50t.v:
- Add top-level differential input ports adc_or_p/n (AD9484 overflow flag,
pads M6/N6) and fpga_adc_clock_p/n (AD9523->ADC sample clock tap, pads
N11/N12, input-only to avoid contention with AD9523 driver).
- Anchor both via IBUFDS (DIFF_TERM=TRUE, IOSTANDARD=LVDS_25) wrapped in
(* DONT_TOUCH = "TRUE" *) so synthesis cannot strip the ports.
- Buffered nets (adc_or_buf, fpga_adc_clock_buf) are intentionally
unconsumed pending a follow-up PR that wires adc_or_buf into the
receive-path status flags (issue: numeric-saturation visibility to MCU)
and decides whether fpga_adc_clock_buf is diagnostic-only or feeds an
MMCM (in which case the buffer will need to move to a clock-capable
path).
Not validated locally: no Verilator / Vivado on the dev host. Requires
report_timing_summary and report_cdc on the remote Vivado 2025.2 host
before bitstream release.
This commit is contained in:
Jason
@@ -18,8 +18,23 @@
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# Bank 35: VCCO = 3.3V (FT2232H USB 2.0 FIFO — 15 signals)
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#
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# DRC Fix History:
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# - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC).
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# Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair.
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# - PLIO-9 (REVERTED): Previously moved clk_120m_dac from C13 (N-type) to
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# D13 (P-type MRCC) to satisfy the MRCC preference. However, a schematic
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# audit (KiCad netlist export from the Eagle schematic, U42 pad->net map)
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# revealed that D13 is UNCONNECTED on the physical PCB. The real
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# /FPGA_DAC_CLOCK net from AD9523 OUT11 lands on C13 (IO_L11N_T1_SRCC_15,
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# N-type). Moved back to C13 and added CLOCK_DEDICATED_ROUTE FALSE,
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# matching the ft_clkout treatment on C4 (N-type MRCC).
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# - Schematic audit added pin constraints for previously-unconstrained
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# signals connected to the FPGA in hardware: ADC_OR_P/N (M6/N6, AD9484
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# overflow flag), /FPGA_ADC_CLOCK_P/N (N11/N12, 400 MHz observation tap
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# of the AD9523->AD9484 sample clock). Added to 50T wrapper as
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# anchored-but-unused inputs to secure pin assignment and prevent
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# accidental future contention; full RTL consumers are a follow-up.
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# - PLIO-9 (original, historical): FT2232H CLKOUT routed to C4
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# (IO_L12N_T1_MRCC_35, N-type). Clock inputs normally use P-type MRCC
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# pins, but IBUFG works correctly on N-type. Demote PLIO-9 to warning
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# in build script.
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# - BIVC-1 / Place 30-372: Bank 14 must have a single VCCO. LVDS_25 forces
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# VCCO=2.5V, so adc_pwdn was changed from LVCMOS33 to LVCMOS25 to match.
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# IBUFDS input buffers are VCCO-independent. BIVC-1 also waived via
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@@ -28,9 +43,6 @@
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# - UCIO/NSTD: Unconstrained ports (FT601 ports inactive with USB_MODE=1,
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# status/debug outputs have no physical pins). Handled with SEVERITY
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# demotion + default IOSTANDARD.
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# - PLIO-9: FT2232H CLKOUT routed to C4 (IO_L12N_T1_MRCC_35, N-type).
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# Clock inputs normally use P-type MRCC pins, but IBUFG works correctly
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# on N-type. Demote PLIO-9 to warning in build script.
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# ============================================================================
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# ============================================================================
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@@ -66,7 +78,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {clk_100m}]
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create_clock -name clk_100m -period 10.0 [get_ports {clk_100m}]
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set_input_jitter [get_clocks clk_100m] 0.1
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# 120MHz DAC Clock (AD9523 OUT11 → FPGA_DAC_CLOCK → Bank 15 MRCC pin D13)
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# 120MHz DAC Clock (AD9523 OUT11 → /FPGA_DAC_CLOCK → Bank 15 pin C13)
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# NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
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# AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
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# uses this clock input for internal DAC data timing only. The RTL port
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@@ -74,12 +86,19 @@ set_input_jitter [get_clocks clk_100m] 0.1
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# physical pin on the 50T board and is left unconnected here. The port
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# CANNOT be removed from the RTL because the 200T board uses it with
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# ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
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# FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
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# Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
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set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
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#
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# PIN: C13 is IO_L11N_T1_SRCC_15 (N-type SRCC). A prior commit attempted to
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# move this to D13 (MRCC P-type) to satisfy PLIO-9, but the schematic audit
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# showed D13 is UNCONNECTED on the PCB — the /FPGA_DAC_CLOCK net physically
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# lands on C13. Moving to D13 made the DAC clock input float. Restored to
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# C13 and forced CLOCK_DEDICATED_ROUTE FALSE (same mechanism as ft_clkout on
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# C4), which routes the IBUFG output through general fabric to a BUFG.
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set_property PACKAGE_PIN C13 [get_ports {clk_120m_dac}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk_120m_dac}]
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create_clock -name clk_120m_dac -period 8.333 [get_ports {clk_120m_dac}]
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set_input_jitter [get_clocks clk_120m_dac] 0.1
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# C13 is N-type SRCC (not dedicated-clock-capable); override the DRC check.
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {clk_120m_dac_IBUF}]
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# ADC DCO Clock (400MHz LVDS — AD9523 OUT5 → AD9484 → FPGA, Bank 14 MRCC)
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# NOTE: LVDS_25 is the only valid differential input standard on 7-series HR
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@@ -283,6 +302,45 @@ set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
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set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
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set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
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# --------------------------------------------------------------------------
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# AD9484 Overflow / Out-Of-Range flag (schematic nets ADC_OR_P / ADC_OR_N)
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# --------------------------------------------------------------------------
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# AD9484 differential OR output on FPGA pads M6 (OR_P) / N6 (OR_N), Bank 14.
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# This is the AD9484's full-scale overflow indicator, useful for AGC /
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# gain-ranging feedback. The 50T RTL wrapper anchors this with an IBUFDS
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# (DONT_TOUCH) so the pads cannot be accidentally driven as outputs (which
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# would cause contention with the AD9484 driver). A future PR should wire
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# the buffered signal into the receive-path status flags.
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set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
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set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
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set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
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# --------------------------------------------------------------------------
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# FPGA observation of AD9523->AD9484 sample clock (/FPGA_ADC_CLOCK_P/N)
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# --------------------------------------------------------------------------
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# AD9523 drives the AD9484 sample clock directly; the same differential
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# pair is tapped to FPGA pads N11 (P) / N12 (N), Bank 14, MRCC-capable.
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# This is an INPUT-ONLY tap (FPGA must never drive these pads — that would
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# contend with the AD9523 driver feeding the ADC). The 50T wrapper anchors
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# with IBUFDS + DONT_TOUCH so the pad assignment is preserved across all
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# synthesis/optimization stages. The buffered net is unconsumed for now;
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# create_clock and clock_groups are deferred until an RTL consumer exists
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# (see commented template below).
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set_property PACKAGE_PIN N11 [get_ports {fpga_adc_clock_p}]
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set_property PACKAGE_PIN N12 [get_ports {fpga_adc_clock_n}]
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set_property IOSTANDARD LVDS_25 [get_ports {fpga_adc_clock_p}]
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set_property IOSTANDARD LVDS_25 [get_ports {fpga_adc_clock_n}]
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set_property DIFF_TERM TRUE [get_ports {fpga_adc_clock_p}]
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# No create_clock here on purpose: the IBUFDS output is unconsumed (anchored
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# via DONT_TOUCH only), so declaring it as a clock would only generate
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# "clock has no registered destinations" warnings. When a follow-up PR adds
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# an actual consumer, add:
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# create_clock -name fpga_adc_clock -period 2.5 [get_ports {fpga_adc_clock_p}]
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# set_input_jitter [get_clocks fpga_adc_clock] 0.05
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# set_clock_groups -asynchronous -group [get_clocks fpga_adc_clock] ...
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# ============================================================================
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# FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
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# ============================================================================
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@@ -347,29 +405,49 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
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# FPGA Write Path (FPGA drives data, FT2232H samples):
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# - Data setup before next CLKOUT rising: t_su = 5.0 ns
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# - Data hold after CLKOUT rising: t_hd = 0.0 ns
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# - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
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# - Output delay min = t_hd = 0.0 ns
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# - Board trace skew budget: ~0.5 ns
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# - Output delay max = t_su + trace_max = 5.0 + 0.5 = 5.5 ns
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# - Output delay min = t_hd - trace_min = 0.0 - 0.0 = 0.0 ns
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#
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# NOTE: Historical XDC used 'period - t_su = 11.667 ns' for output_delay -max,
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# which is the wrong interpretation: set_output_delay takes the external setup
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# requirement (+trace), not the remaining timing budget. The old value forced
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# Vivado to close a path assuming FT2232H requires 11.667 ns of setup, which
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# it does not, and caused WNS=-5.350 ns failures on ft_data/ft_rd_n/ft_wr_n/
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# ft_oe_n/ft_siwu paths given the 5.513 ns clock insertion delay on the
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# non-dedicated C4 routing.
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# --------------------------------------------------------------------------
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# Input delays: FT2232H → FPGA (data bus and status signals)
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#
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# -min revision (Build N+1): was 0.0 ns, now 1.0 ns.
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# Rationale: set_input_delay -min is the EARLIEST time data can change at the
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# FPGA pin after the launch clock edge, i.e. FT2232H Tco_min + trace_min.
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# Setting -min 0.0 claimed data could change simultaneously with the clock
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# edge, which is pessimistically tight for hold analysis and caused a
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# -0.079 ns hold violation on ft_rxf_n → FSM_sequential_wr_state in Build N
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# (due to 2.895 ns clock insertion delay on non-dedicated C4 routing).
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# FT2232H Sync FIFO Tco is spec'd 1–4 ns; using 1.0 ns is conservative and
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# still covers worst-case silicon. Invariant preserved: hold_margin =
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# Tco_min + trace_min - clk_insertion_delay - Th_fpga ≥ 0.
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set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
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set_input_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_data[*]}]
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set_input_delay -clock [get_clocks ft_clkout] -min 1.0 [get_ports {ft_data[*]}]
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set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
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set_input_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_rxf_n}]
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set_input_delay -clock [get_clocks ft_clkout] -min 1.0 [get_ports {ft_rxf_n}]
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set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
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set_input_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_txe_n}]
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set_input_delay -clock [get_clocks ft_clkout] -min 1.0 [get_ports {ft_txe_n}]
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# Output delays: FPGA → FT2232H (control strobes and data bus when writing)
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set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_data[*]}]
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set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_rd_n}]
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set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_wr_n}]
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set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_oe_n}]
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set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_siwu}]
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set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_data[*]}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_data[*]}]
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set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_rd_n}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_rd_n}]
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set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_wr_n}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_wr_n}]
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set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_oe_n}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_oe_n}]
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set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_siwu}]
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set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_siwu}]
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# ============================================================================
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# STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
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@@ -411,24 +489,42 @@ set_false_path -from [get_ports {stm32_mixers_enable}]
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set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]
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# --------------------------------------------------------------------------
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# Clock Domain Crossing false paths
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# Clock Domain Crossing — asynchronous clock groups
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#
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# Rationale: prefer `set_clock_groups -asynchronous` over pairwise
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# `set_false_path -from CLK -to CLK`. The latter is an STA antipattern:
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# it disables *all* paths between the two domains, including the
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# synchronizer paths themselves and any future inadvertent crossings,
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# which can mask real CDC bugs that only show up at temperature/voltage
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# corners. Clock-groups is the idiomatic way to declare domains async
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# while still letting STA flag newly-introduced unrelated paths.
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#
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# Register-level false_paths (e.g. reset_sync_reg above) remain
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# appropriate — those restrict the waiver to specific, audited endpoints.
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#
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# Groups declared here mirror the pairwise false_paths that existed
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# previously; no new pair is declared async.
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# --------------------------------------------------------------------------
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# clk_100m ↔ adc_dco_p (400 MHz): DDC has internal CDC synchronizers
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set_false_path -from [get_clocks clk_100m] -to [get_clocks adc_dco_p]
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set_false_path -from [get_clocks adc_dco_p] -to [get_clocks clk_100m]
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set_clock_groups -asynchronous \
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-group [get_clocks clk_100m] \
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-group [get_clocks adc_dco_p]
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# clk_100m ↔ clk_120m_dac: CDC via synchronizers in radar_system_top
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set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_120m_dac]
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set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m]
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set_clock_groups -asynchronous \
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-group [get_clocks clk_100m] \
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-group [get_clocks clk_120m_dac]
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# FT2232H CDC: clk_100m ↔ ft_clkout (60 MHz), toggle CDC in RTL
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set_false_path -from [get_clocks clk_100m] -to [get_clocks ft_clkout]
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set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
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set_clock_groups -asynchronous \
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-group [get_clocks clk_100m] \
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-group [get_clocks ft_clkout]
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# FT2232H CDC: clk_120m_dac ↔ ft_clkout (no direct crossing, but belt-and-suspenders)
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set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
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set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
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set_clock_groups -asynchronous \
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-group [get_clocks clk_120m_dac] \
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-group [get_clocks ft_clkout]
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# ============================================================================
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# PHYSICAL CONSTRAINTS
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@@ -62,6 +62,20 @@ module radar_system_top_50t (
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input wire adc_dco_n,
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output wire adc_pwdn,
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// ----- AD9484 overflow flag (differential) -----
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// Schematic pads M6 (OR_P) / N6 (OR_N). Anchored-only for now; a future
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// PR will wire this into the receive-path status flags for AGC feedback.
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input wire adc_or_p,
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input wire adc_or_n,
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// ----- Tap of AD9523 -> AD9484 sample clock (differential) -----
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// Schematic pads N11 (P) / N12 (N). Must remain input-only — driving
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// these pads as outputs would contend with the AD9523 driver feeding
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// the ADC. Anchored with an IBUFDS (DONT_TOUCH) below; buffered net is
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// unconsumed pending a follow-up PR.
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input wire fpga_adc_clock_p,
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input wire fpga_adc_clock_n,
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// ===== STM32 Control (Bank 15: 3.3V) =====
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input wire stm32_new_chirp,
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input wire stm32_new_elevation,
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@@ -84,6 +98,38 @@ module radar_system_top_50t (
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output wire gpio_dig7 // DIG_7 (H12→PD15): reserved
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);
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// =====================================================================
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// Anchored-but-unused schematic inputs (secured via IBUFDS + DONT_TOUCH)
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// =====================================================================
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// Without these buffer instantiations, synthesis would remove the
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// orphan input ports (UCIO / NSTD warnings) and the XDC pin constraints
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||||
// would fail to bind. DONT_TOUCH forces Vivado to retain the buffer
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// primitives and their package-pin connections across all optimization
|
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// stages. The buffered nets are intentionally left unconsumed here;
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// they will be wired into the RTL in a follow-up PR once the ADC
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// status-flag and sample-clock-tap features are implemented.
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(* DONT_TOUCH = "TRUE" *) wire adc_or_buf;
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(* DONT_TOUCH = "TRUE" *) IBUFDS #(
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.DIFF_TERM ("TRUE"),
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.IBUF_LOW_PWR("FALSE"),
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.IOSTANDARD ("LVDS_25")
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||||
) u_ibufds_adc_or (
|
||||
.O (adc_or_buf),
|
||||
.I (adc_or_p),
|
||||
.IB (adc_or_n)
|
||||
);
|
||||
|
||||
(* DONT_TOUCH = "TRUE" *) wire fpga_adc_clock_buf;
|
||||
(* DONT_TOUCH = "TRUE" *) IBUFDS #(
|
||||
.DIFF_TERM ("TRUE"),
|
||||
.IBUF_LOW_PWR("FALSE"),
|
||||
.IOSTANDARD ("LVDS_25")
|
||||
) u_ibufds_fpga_adc_clk (
|
||||
.O (fpga_adc_clock_buf),
|
||||
.I (fpga_adc_clock_p),
|
||||
.IB (fpga_adc_clock_n)
|
||||
);
|
||||
|
||||
// ===== Tie-off wires for unconstrained FT601 inputs (inactive with USB_MODE=1) =====
|
||||
wire ft601_txe_tied = 1'b0;
|
||||
wire ft601_rxf_tied = 1'b0;
|
||||
|
||||
Reference in New Issue
Block a user