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Add TE0713/TE0701 alternate dev target for in-stock SoM path

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This commit is contained in:
Jason
2026-03-18 15:01:55 +02:00
parent 25a739df07
commit 967ce179eb
4 changed files with 163 additions and 2 deletions
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9_Firmware/9_2_FPGA/constraints/README.md
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@@ -1,14 +1,15 @@
# AERIS-10 FPGA Constraint Files
## Three Targets
## Four Targets
| File | Device | Package | Purpose |
|------|--------|---------|---------|
| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | Upstream author's board (copy of `cntrt.xdc`) |
| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Production board (new PCB design) |
| `te0712_te0701_minimal.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Trenz dev split target (minimal clock/reset + LEDs/status) |
| `te0713_te0701_minimal.xdc` | XC7A200T-2FBG484C | FBG484 (484-ball BGA) | Trenz alternate SoM target (minimal clock + FMC status outputs) |
## Why Three Files
## Why Four Files
The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production
AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources.
@@ -20,6 +21,10 @@ pinout and peripherals. The dev target is split into its own top wrapper
(`radar_system_top_te0712_dev.v`) and minimal constraints file to avoid accidental mixing
of production pin assignments during bring-up.
The Trenz TE0713/TE0701 path supports situations where TE0712 lead time is prohibitive.
TE0713 uses XC7A200T-2FBG484C (commercial temp grade) and requires separate clock mapping,
so it has its own dev top and XDC.
## Bank Voltage Assignments
### XC7A50T-FTG256 (Upstream)
@@ -73,6 +78,9 @@ read_xdc constraints/xc7a50t_ftg256.xdc
# For Trenz TE0712/TE0701 split target:
read_xdc constraints/te0712_te0701_minimal.xdc
# For Trenz TE0713/TE0701 split target:
read_xdc constraints/te0713_te0701_minimal.xdc
```
## Top Modules by Target
@@ -82,6 +90,7 @@ read_xdc constraints/te0712_te0701_minimal.xdc
| Upstream FTG256 | `radar_system_top` | Legacy board support |
| Production FBG484 | `radar_system_top` | Main AERIS-10 board |
| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | Minimal bring-up wrapper while pinout/peripherals are migrated |
| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | Alternate SoM wrapper (TE0713 clock mapping) |
## Trenz Split Status
@@ -114,6 +123,9 @@ Use the dedicated script for the split dev target:
```bash
vivado -mode batch -source scripts/build_te0712_dev.tcl
# TE0713/TE0701 target
vivado -mode batch -source scripts/build_te0713_dev.tcl
```
Outputs:
@@ -122,6 +134,12 @@ Outputs:
- Top module: `radar_system_top_te0712_dev`
- Constraint file: `constraints/te0712_te0701_minimal.xdc`
TE0713 outputs:
- Project directory: `vivado_te0713_dev/`
- Reports: `vivado_te0713_dev/reports/`
- Top module: `radar_system_top_te0713_dev`
- Constraint file: `constraints/te0713_te0701_minimal.xdc`
## Notes
- The production XDC pin assignments are **recommended** for the new PCB.
9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc
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# ============================================================================
# AERIS-10 TE0713/TE0701 DEV TARGET (MINIMAL SPLIT)
# ============================================================================
# Target part: XC7A200T-2FBG484C (TE0713-03-82C46-A)
# Board: TE0701-06 carrier
#
# This XDC is intentionally minimal and is used with:
# top = radar_system_top_te0713_dev
#
# Notes:
# - TE0713 clock routing differs from TE0712. This target uses FIFO0CLK net at
# package pin U20 as primary fabric clock for initial bring-up.
# - No external reset is used in this minimal top to avoid uncertain reset pin
# assumptions between TE0712/TE0713 revisions.
# ============================================================================
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
# Clock IOSTANDARD
set_property IOSTANDARD LVCMOS15 [get_ports {clk_100m}]
# Status/output IO standards
# These outputs are exported to TE0701 FMC LA lines (not onboard LEDs).
# Assumption: FMC VADJ/VCCIO16 is set for 2.5V signaling.
set_property IOSTANDARD LVCMOS25 [get_ports {user_led[*]}]
set_property IOSTANDARD LVCMOS25 [get_ports {system_status[*]}]
# Clock constraint (TE0713 FIFO0CLK source observed as 50 MHz)
create_clock -name clk_100m -period 20.000 [get_ports {clk_100m}]
set_input_jitter [get_clocks clk_100m] 0.100
# --------------------------------------------------------------------------
# TE0713 package pin mapping
# --------------------------------------------------------------------------
set_property PACKAGE_PIN U20 [get_ports {clk_100m}]
# --------------------------------------------------------------------------
# TE0701 FMC export mapping (B16 bank mappings align with TE0712 flow)
# user_led[0..3] -> FMC_LA14_N/P, FMC_LA13_N/P
# system_status[] -> FMC_LA5_N/P, FMC_LA6_N/P
# --------------------------------------------------------------------------
set_property PACKAGE_PIN A19 [get_ports {user_led[0]}]
set_property PACKAGE_PIN A18 [get_ports {user_led[1]}]
set_property PACKAGE_PIN F20 [get_ports {user_led[2]}]
set_property PACKAGE_PIN F19 [get_ports {user_led[3]}]
set_property PACKAGE_PIN F18 [get_ports {system_status[0]}]
set_property PACKAGE_PIN E18 [get_ports {system_status[1]}]
set_property PACKAGE_PIN C22 [get_ports {system_status[2]}]
set_property PACKAGE_PIN B22 [get_ports {system_status[3]}]
# --------------------------------------------------------------------------
# Keep implementation checks strict.
# report_timing_summary -report_unconstrained
# report_drc
9_Firmware/9_2_FPGA/radar_system_top_te0713_dev.v
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`timescale 1ns / 1ps
module radar_system_top_te0713_dev (
input wire clk_100m,
output wire [3:0] user_led,
output wire [3:0] system_status
);
wire clk_100m_buf;
reg [31:0] hb_counter;
BUFG bufg_100m (
.I(clk_100m),
.O(clk_100m_buf)
);
always @(posedge clk_100m_buf) begin
hb_counter <= hb_counter + 1'b1;
end
assign user_led[0] = hb_counter[24];
assign user_led[1] = hb_counter[25];
assign user_led[2] = hb_counter[26];
assign user_led[3] = hb_counter[27];
assign system_status[0] = hb_counter[23];
assign system_status[1] = hb_counter[24];
assign system_status[2] = hb_counter[25];
assign system_status[3] = hb_counter[26];
endmodule
9_Firmware/9_2_FPGA/scripts/build_te0713_dev.tcl
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# build_te0713_dev.tcl
#
# Vivado batch build for Trenz TE0713/TE0701 split target.
#
# Usage:
# vivado -mode batch -source scripts/build_te0713_dev.tcl
set script_dir [file dirname [file normalize [info script]]]
set project_root [file normalize [file join $script_dir ".."]]
set project_name "aeris10_te0713_dev"
set build_dir [file join $project_root "vivado_te0713_dev"]
set reports_dir [file join $build_dir "reports"]
set top_file [file join $project_root "radar_system_top_te0713_dev.v"]
set xdc_file [file join $project_root "constraints" "te0713_te0701_minimal.xdc"]
file mkdir $build_dir
file mkdir $reports_dir
create_project -force $project_name $build_dir -part xc7a200tfbg484-2
set_property target_language Verilog [current_project]
add_files -norecurse $top_file
add_files -fileset constrs_1 -norecurse $xdc_file
set_property top radar_system_top_te0713_dev [current_fileset]
update_compile_order -fileset sources_1
puts "INFO: Launching implementation to bitstream..."
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1
set impl_status [get_property STATUS [get_runs impl_1]]
puts "INFO: impl_1 status: $impl_status"
if {![string match "*Complete*" $impl_status]} {
error "Implementation did not complete successfully. Status: $impl_status"
}
open_run impl_1
report_clocks -file [file join $reports_dir "clocks.rpt"]
report_clock_interaction -file [file join $reports_dir "clock_interaction.rpt"]
report_timing_summary -report_unconstrained -max_paths 100 -file [file join $reports_dir "timing_summary.rpt"]
report_cdc -details -file [file join $reports_dir "cdc.rpt"]
report_exceptions -file [file join $reports_dir "exceptions.rpt"]
report_drc -file [file join $reports_dir "drc.rpt"]
report_utilization -file [file join $reports_dir "utilization.rpt"]
set bit_file [get_property BITSTREAM.FILE [current_design]]
puts "INFO: Build complete."
puts "INFO: Bitstream: $bit_file"
puts "INFO: Reports: $reports_dir"