fix(fpga): F-0.1 wire AD9484 OR overrange pin into diagnostics

The AD9484 OR (overrange) LVDS pair is routed on the 50T main board to
xc7a50t-ftg256 bank-14 pins M6/N6 but was previously left unconnected at
the top level. Plumb it through the full stack so saturation at the raw
ADC boundary shows up in the existing overflow aggregation:

- ad9484_interface_400m: add adc_or_p/n inputs, IBUFDS + IDDR capture of
  both phases in the BUFIO domain, re-register into the clk_400m BUFG
  domain, OR rise|fall into adc_overrange_400m output.
- radar_receiver_final: stickify adc_overrange_400m in clk_400m, CDC to
  clk_100m via a 2FF ASYNC_REG chain (same reasoning as F-1.2's
  cdc_cic_fir_overrun — single-bit, latched low→high, GPIO-class
  diagnostic), OR into the existing ddc_overflow_any aggregation.
- radar_system_top: expose adc_or_p/n top-level ports and pass through.
- xc7a50t_ftg256.xdc: anchor M6/N6 as LVDS_25 DIFF_TERM, with the same
  DCO-relative input-delay constraints as adc_d_p[*].
- xc7a200t_fbg484.xdc: IOSTANDARD/DIFF_TERM set; PACKAGE_PIN left as a
  documented TODO — the 200T dev-board schematic has not been checked
  and the 200T build will need the anchor filled in before place/route.

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -67,6 +67,9 @@ module radar_system_top (
     input wire [7:0] adc_d_n,            // ADC Data N (LVDS)
     input wire adc_dco_p,                 // Data Clock Output P (400MHz LVDS)
     input wire adc_dco_n,                 // Data Clock Output N (400MHz LVDS)
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
+    input wire adc_or_p,
+    input wire adc_or_n,
     output wire adc_pwdn,                  // ADC Power Down
     
     // ========== STM32 CONTROL INTERFACES ==========
@@ -526,6 +529,8 @@ radar_receiver_final rx_inst (
     .adc_d_n(adc_d_n),
     .adc_dco_p(adc_dco_p),
     .adc_dco_n(adc_dco_n),
+    .adc_or_p(adc_or_p),
+    .adc_or_n(adc_or_n),
     .adc_pwdn(adc_pwdn),
     
     // Doppler Outputs