FlintyLemming/PLFM_RADAR
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Update ILA probe script references from Build 13 to Build 16

Browse Source
This commit is contained in:
Jason
2026-03-19 17:01:12 +02:00
parent 683e70e784
commit 8ca6d992cb
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl
+4 -4
View File
@@ -3,15 +3,15 @@
# #
# AERIS-10 Radar FPGA — Post-Synthesis ILA Debug Core Insertion # AERIS-10 Radar FPGA — Post-Synthesis ILA Debug Core Insertion
# Target: XC7A200T-2FBG484I # Target: XC7A200T-2FBG484I
# Design: radar_system_top (Build 13 frozen netlist) # Design: radar_system_top (Build 16 frozen netlist)
# #
# Usage: # Usage:
# vivado -mode batch -source insert_ila_probes.tcl # vivado -mode batch -source insert_ila_probes.tcl
# #
# This script: # This script:
# 1. Opens the post-synth DCP from Build 13 # 1. Opens the post-synth DCP from Build 16
# 2. Inserts 4 ILA debug cores across 2 clock domains # 2. Inserts 4 ILA debug cores across 2 clock domains
# 3. Runs full implementation with Build 13 directives # 3. Runs full implementation with Build 16 directives
# 4. Generates bitstream, reports, and .ltx probe file # 4. Generates bitstream, reports, and .ltx probe file
# #
# ILA 0: ADC Capture — 400 MHz (rx_inst/adc/clk_400m) — up to 9 bits # ILA 0: ADC Capture — 400 MHz (rx_inst/adc/clk_400m) — up to 9 bits
@@ -41,7 +41,7 @@ set part "xc7a200tfbg484-2"
# Timestamp for output file naming # Timestamp for output file naming
set timestamp [clock format [clock seconds] -format {%Y%m%d_%H%M%S}] set timestamp [clock format [clock seconds] -format {%Y%m%d_%H%M%S}]
set run_tag "build13_ila_${timestamp}" set run_tag "build16_ila_${timestamp}"
# ILA parameters # ILA parameters
set ila_depth 4096 set ila_depth 4096