From 8b4de5f9ee734fa64e32110561495be493494554 Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Mon, 20 Apr 2026 23:28:58 +0545
Subject: [PATCH] fix(fpga): extend ADC hold waiver to include adc_or_p (F-0.1
 follow-up)
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adc_or_p (overrange pin, added in commit 70067c6 for audit finding F-0.1)
uses the same IBUFDS→BUFIO source-synchronous capture topology as the 8
data pins adc_d_p[*]. STA reports identical -1.913 ns hold on this path
for the same reason (clock insertion ~4.0 ns via BUFIO vs data IBUFDS
~0.9 ns). External PCB layout guarantees hold, not FPGA clock tree.

Extends the existing adc_d_p[*] false_path waiver to cover adc_or_p.
Post-route now clean: WNS +0.034 ns, WHS positive.
---
 9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
index 518f4da..e149ec5 100644
--- a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
@@ -89,7 +89,11 @@ set_false_path -through [get_pins -hierarchical -filter {REF_PIN_NAME == LOCKED}
 #
 # Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
 # for source-synchronous LVDS ADC interfaces using BUFIO capture.
-set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
+# adc_or_p (AD9484 overrange, audit F-0.1) shares the same IBUFDS→BUFIO
+# source-synchronous capture topology as adc_d_p[*] — same ~1.9 ns STA hold
+# violation for the same reason (BUFIO clock insertion ~4 ns vs data IBUFDS
+# ~0.9 ns), resolved by the same external-timing argument.
+set_false_path -hold -from [get_ports {adc_d_p[*] adc_or_p}] -to [get_clocks adc_dco_p]
 
 # --------------------------------------------------------------------------
 # Timing margin for 400 MHz critical paths