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Open-Source Phased Array Radar

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Engineering Documentation Site

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This site tracks architecture, validated implementation baselines, constraint cleanup progress, and pre-hardware bring-up readiness for AERIS-10.

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Tracked Timing Baseline

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WNS +0.058 ns

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WHS +0.068, WPWS +0.684 after validated Build 16 XDC port

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Regression Status

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MCU 15 / 15, FPGA 18 / 18

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Host firmware regression plus FPGA unit and integration suites passing

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Methodology State

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XDCB-5 = 0

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Single documented TIMING-18 residue on `ft601_txe` async observation

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Current Phase

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Pre-Hardware Readiness

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Board-arrival smoke test, artifact inventory, and open-risk tracking prepared

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What changed recently

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  • Ported the validated Build 16 production-target XDC cleanup into the tracked repository.
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  • Preserved positive post-route timing while clearing XDCB-5 and reducing methodology residue to a single documented item.
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  • Validated the tracked branch with MCU host regression and FPGA regression/integration suites.
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  • Refreshed the bring-up documentation into a pre-arrival readiness package for the FPGA module and carrier board.
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  • Kept upstream ADAR1000 bulk imports out of the baseline pending selective, justified reuse only.
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