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Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)

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Register map: 0x10-0x15 chirp timing overrides, 0xFF status readback,
0x03 CFAR threshold now wired to actual compare, 0x04 stream control
gates USB write FSM. Status readback sends 7-word packet (0xBB header,
5 status words, 0x55 footer) via toggle CDC.

radar_mode_controller: 6 cfg_* input ports replace hardcoded parameters.
usb_data_interface: stream_control CDC, status_request toggle CDC,
  SEND_STATUS state (3'd7), stream gating in IDLE/HEADER/RANGE/DOPPLER.
radar_system_top: 6 host registers + command decode for 0x10-0x15/0xFF.
radar_receiver_final: 6 host_* timing passthrough ports.

Testbench coverage: RMC 81 checks (+TG16 runtime reconfig), USB 77
checks (+TG15 stream gating, TG16 status readback, TG17 chirp opcodes).
Fixed iverilog 13.0 forward-ref for status_req_toggle_100m.
This commit is contained in:
Jason
2026-03-19 23:54:48 +02:00
parent d2f20f5c15
commit 7cdfa486e5
8 changed files with 604 additions and 26 deletions
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9_Firmware/9_2_FPGA/tb/tb_radar_mode_controller.v
+97
View File
@@ -26,6 +26,14 @@ module tb_radar_mode_controller;
reg stm32_new_azimuth;
reg trigger;
// Gap 2: Runtime-configurable timing inputs
reg [15:0] cfg_long_chirp_cycles;
reg [15:0] cfg_long_listen_cycles;
reg [15:0] cfg_guard_cycles;
reg [15:0] cfg_short_chirp_cycles;
reg [15:0] cfg_short_listen_cycles;
reg [5:0] cfg_chirps_per_elev;
wire use_long_chirp;
wire mc_new_chirp;
wire mc_new_elevation;
@@ -78,6 +86,14 @@ module tb_radar_mode_controller;
.stm32_new_elevation(stm32_new_elevation),
.stm32_new_azimuth (stm32_new_azimuth),
.trigger (trigger),
// Gap 2: Runtime-configurable timing inputs
.cfg_long_chirp_cycles (cfg_long_chirp_cycles),
.cfg_long_listen_cycles (cfg_long_listen_cycles),
.cfg_guard_cycles (cfg_guard_cycles),
.cfg_short_chirp_cycles (cfg_short_chirp_cycles),
.cfg_short_listen_cycles(cfg_short_listen_cycles),
.cfg_chirps_per_elev (cfg_chirps_per_elev),
// Outputs
.use_long_chirp (use_long_chirp),
.mc_new_chirp (mc_new_chirp),
.mc_new_elevation (mc_new_elevation),
@@ -114,6 +130,13 @@ module tb_radar_mode_controller;
stm32_new_elevation = 0;
stm32_new_azimuth = 0;
trigger = 0;
// Gap 2: Set cfg_* to simulation parameter defaults
cfg_long_chirp_cycles = SIM_LONG_CHIRP;
cfg_long_listen_cycles = SIM_LONG_LISTEN;
cfg_guard_cycles = SIM_GUARD;
cfg_short_chirp_cycles = SIM_SHORT_CHIRP;
cfg_short_listen_cycles = SIM_SHORT_LISTEN;
cfg_chirps_per_elev = SIM_CHIRPS;
repeat (4) @(posedge clk);
reset_n = 1;
@(posedge clk); #1;
@@ -629,6 +652,80 @@ module tb_radar_mode_controller;
$display(" chirp_count after 4th toggle: %0d (expect 0)", chirp_count);
check(chirp_count === 6'd0, "Persistence: chirp_count wraps to 0 at 4th toggle");
// ════════════════════════════════════════════════════════
// TEST GROUP 16: Runtime Timing Reconfiguration (Gap 2)
// Verify that changing cfg_* mid-simulation changes timing.
// We halve the long chirp duration and verify the chirp
// completes in fewer cycles.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 16: Runtime Timing Reconfiguration (Gap 2) ---");
apply_reset;
mode = 2'b01; // auto-scan
// Let the first chirp start (S_IDLE -> S_LONG_CHIRP)
@(posedge clk); #1;
check(scanning === 1'b1, "Reconfig: auto-scan started");
check(use_long_chirp === 1'b1, "Reconfig: starts with long chirp");
// Wait ~half the default long chirp time to confirm we're still in S_LONG_CHIRP
repeat (SIM_LONG_CHIRP / 2) @(posedge clk); #1;
check(uut.scan_state === 3'd1, "Reconfig: still in S_LONG_CHIRP at midpoint");
// Now change cfg_long_chirp_cycles to a much shorter value mid-scan.
// The timer is already at ~SIM_LONG_CHIRP/2, so setting cycles to
// (SIM_LONG_CHIRP/2 - 2) means the timer already exceeds the new limit
// and the FSM will advance on the next cycle.
cfg_long_chirp_cycles = SIM_LONG_CHIRP / 2 - 2;
repeat (2) @(posedge clk); #1;
// The FSM should have transitioned past S_LONG_CHIRP
check(uut.scan_state !== 3'd1, "Reconfig: FSM left S_LONG_CHIRP after shortening cycles");
// Restore default and verify scan continues
cfg_long_chirp_cycles = SIM_LONG_CHIRP;
repeat (10) @(posedge clk); #1;
check(scanning === 1'b1, "Reconfig: scan continues after restoring default");
// Test runtime chirps_per_elev change:
// Reset and set chirps_per_elev to 2 (instead of default 4)
apply_reset;
cfg_chirps_per_elev = 6'd2;
mode = 2'b01; // auto-scan
mc_new_chirp_prev = 0;
chirp_toggles = 0;
elevation_toggles = 0;
@(posedge clk); #1;
mc_new_chirp_prev = mc_new_chirp;
mc_new_elevation_prev = mc_new_elevation;
chirp_toggles = 1; // initial toggle
// Run enough cycles for a few chirps + elevation advance
// With 2 chirps/elev: each chirp ~342 cycles (30+137+175+5+175)
// 2 chirps = ~684 cycles, then elevation advance
for (i = 0; i < 2000; i = i + 1) begin
@(posedge clk); #1;
if (mc_new_chirp !== mc_new_chirp_prev)
chirp_toggles = chirp_toggles + 1;
if (mc_new_elevation !== mc_new_elevation_prev)
elevation_toggles = elevation_toggles + 1;
mc_new_chirp_prev = mc_new_chirp;
mc_new_elevation_prev = mc_new_elevation;
end
$display(" chirp_toggles=%0d elevation_toggles=%0d (cfg_chirps_per_elev=2)",
chirp_toggles, elevation_toggles);
// With 2 chirps/elev, we should get elevation toggles at every 2 chirps
check(elevation_toggles >= 1,
"Reconfig: elevation advances with cfg_chirps_per_elev=2");
// Verify the ratio: chirp_toggles should be ~2x elevation_toggles
// (first elevation has 2 chirps, then toggle. Second has 2 chirps, then toggle, etc.)
check(chirp_toggles >= 2 * elevation_toggles,
"Reconfig: chirp/elevation ratio consistent with cfg_chirps_per_elev=2");
// Restore defaults
cfg_chirps_per_elev = SIM_CHIRPS;
// ════════════════════════════════════════════════════════
// Summary
// ════════════════════════════════════════════════════════
9_Firmware/9_2_FPGA/tb/tb_radar_receiver_final.v
+18 -1
View File
@@ -132,7 +132,24 @@ radar_receiver_final dut (
.doppler_output(doppler_output),
.doppler_valid(doppler_valid),
.doppler_bin(doppler_bin),
.range_bin(range_bin_out)
.range_bin(range_bin_out),
// Range profile outputs (unused in this TB)
.range_profile_i_out(),
.range_profile_q_out(),
.range_profile_valid_out(),
// Host command inputs (Gap 4) — default auto-scan, no trigger
.host_mode(2'b01),
.host_trigger(1'b0),
// Gap 2: Host-configurable chirp timing — match defparam overrides below
.host_long_chirp_cycles(16'd500),
.host_long_listen_cycles(16'd2000),
.host_guard_cycles(16'd500),
.host_short_chirp_cycles(16'd50),
.host_short_listen_cycles(16'd1000),
.host_chirps_per_elev(6'd32)
);
// ============================================================================
9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v
+228 -2
View File
@@ -13,7 +13,8 @@ module tb_usb_data_interface;
S_SEND_DOPPLER = 3'd3,
S_SEND_DETECT = 3'd4,
S_SEND_FOOTER = 3'd5,
S_WAIT_ACK = 3'd6;
S_WAIT_ACK = 3'd6,
S_SEND_STATUS = 3'd7; // Gap 2: status readback
// ── Signals ────────────────────────────────────────────────
reg clk;
@@ -59,6 +60,19 @@ module tb_usb_data_interface;
wire [7:0] cmd_addr;
wire [15:0] cmd_value;
// Gap 2: Stream control + status readback inputs
reg [2:0] stream_control;
reg status_request;
reg [15:0] status_cfar_threshold;
reg [2:0] status_stream_ctrl;
reg [1:0] status_radar_mode;
reg [15:0] status_long_chirp;
reg [15:0] status_long_listen;
reg [15:0] status_guard;
reg [15:0] status_short_chirp;
reg [15:0] status_short_listen;
reg [5:0] status_chirps_per_elev;
// ── Clock generators (asynchronous) ────────────────────────
always #(CLK_PERIOD / 2) clk = ~clk;
always #(FT_CLK_PERIOD / 2) ft601_clk_in = ~ft601_clk_in;
@@ -95,7 +109,20 @@ module tb_usb_data_interface;
.cmd_valid (cmd_valid),
.cmd_opcode (cmd_opcode),
.cmd_addr (cmd_addr),
.cmd_value (cmd_value)
.cmd_value (cmd_value),
// Gap 2: Stream control + status readback
.stream_control (stream_control),
.status_request (status_request),
.status_cfar_threshold (status_cfar_threshold),
.status_stream_ctrl (status_stream_ctrl),
.status_radar_mode (status_radar_mode),
.status_long_chirp (status_long_chirp),
.status_long_listen (status_long_listen),
.status_guard (status_guard),
.status_short_chirp (status_short_chirp),
.status_short_listen (status_short_listen),
.status_chirps_per_elev(status_chirps_per_elev)
);
// ── Test bookkeeping ───────────────────────────────────────
@@ -139,6 +166,18 @@ module tb_usb_data_interface;
ft601_swb = 2'b00;
host_data_drive = 32'h0;
host_data_drive_en = 0;
// Gap 2: Stream control defaults (all streams enabled)
stream_control = 3'b111;
status_request = 0;
status_cfar_threshold = 16'd10000;
status_stream_ctrl = 3'b111;
status_radar_mode = 2'b00;
status_long_chirp = 16'd3000;
status_long_listen = 16'd13700;
status_guard = 16'd17540;
status_short_chirp = 16'd50;
status_short_listen = 16'd17450;
status_chirps_per_elev = 6'd32;
repeat (6) @(posedge ft601_clk_in);
reset_n = 1;
repeat (2) @(posedge ft601_clk_in);
@@ -721,6 +760,193 @@ module tb_usb_data_interface;
check(cmd_value === 16'h0002,
"Read after write: cmd_value=0x0002");
// ════════════════════════════════════════════════════════
// TEST GROUP 15: Stream Control Gating (Gap 2)
// Verify that disabling individual streams causes the write
// FSM to skip those data phases.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 15: Stream Control Gating (Gap 2) ---");
// 15a: Disable doppler stream (stream_control = 3'b101 = range + cfar only)
apply_reset;
ft601_txe = 0;
stream_control = 3'b101; // range + cfar, no doppler
// Wait for CDC propagation (2-stage sync)
repeat (6) @(posedge ft601_clk_in);
// Drive range valid — this should trigger the write FSM
assert_range_valid(32'hAA11_BB22);
// FSM: IDLE -> SEND_HEADER -> SEND_RANGE_DATA (doppler disabled) -> SEND_DETECTION_DATA -> SEND_FOOTER
// With ft601_txe=0, SEND_RANGE completes in 4 cycles so we may not catch it.
// Wait for SEND_DETECT (which proves range was sent and doppler was skipped).
wait_for_state(S_SEND_DETECT, 200);
#1;
check(uut.current_state === S_SEND_DETECT,
"Stream gate: reached SEND_DETECT (range sent, doppler skipped)");
pulse_cfar_once(1'b1);
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Stream gate: packet completed without doppler");
// 15b: Disable all streams (stream_control = 3'b000)
// With no streams enabled, a range_valid pulse should NOT trigger the write FSM.
apply_reset;
ft601_txe = 0;
stream_control = 3'b000;
repeat (6) @(posedge ft601_clk_in);
// Assert range_valid — FSM should stay in IDLE
@(posedge clk);
range_profile = 32'hDEAD_DEAD;
range_valid = 1;
repeat (3) @(posedge ft601_clk_in);
@(posedge clk);
range_valid = 0;
// Wait a few more cycles for any CDC propagation
repeat (10) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_IDLE,
"Stream gate: FSM stays IDLE when all streams disabled");
// 15c: Restore all streams
stream_control = 3'b111;
repeat (6) @(posedge ft601_clk_in);
// ════════════════════════════════════════════════════════
// TEST GROUP 16: Status Readback (Gap 2)
// Verify that pulsing status_request triggers a 7-word
// status response via the SEND_STATUS state.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 16: Status Readback (Gap 2) ---");
apply_reset;
ft601_txe = 0;
// Set known status input values
status_cfar_threshold = 16'hABCD;
status_stream_ctrl = 3'b101;
status_radar_mode = 2'b01;
status_long_chirp = 16'd3000;
status_long_listen = 16'd13700;
status_guard = 16'd17540;
status_short_chirp = 16'd50;
status_short_listen = 16'd17450;
status_chirps_per_elev = 6'd32;
// Pulse status_request (1 cycle in clk domain — toggles status_req_toggle_100m)
@(posedge clk);
status_request = 1;
@(posedge clk);
status_request = 0;
// Wait for toggle CDC propagation to ft601_clk domain
// (2-stage sync + edge detect = ~3-4 ft601_clk cycles)
repeat (8) @(posedge ft601_clk_in); #1;
// The write FSM should enter SEND_STATUS
// Give it time to start (IDLE sees status_req_ft601)
wait_for_state(S_SEND_STATUS, 20);
#1;
check(uut.current_state === S_SEND_STATUS,
"Status readback: FSM entered SEND_STATUS");
// The SEND_STATUS state sends 7 words (idx 0-6):
// idx 0: 0xBB header, idx 1-5: status_words[0-4], idx 6: 0x55 footer
// After idx 6 it transitions to WAIT_ACK -> IDLE.
// Since ft601_txe=0, all 7 words should stream without stall.
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Status readback: returned to IDLE after 7-word response");
// Verify the status snapshot was captured correctly.
// status_words[0] = {0xFF, 3'b000, mode[1:0], 5'b0, stream_ctrl[2:0], cfar_threshold[15:0]}
// = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
// = 0xFF_09_05_ABCD... let's compute:
// Byte 3: 0xFF = 8'hFF
// Byte 2: {3'b000, 2'b01} = 5'b00001 + 3 high bits of next field...
// Actually the packing is: {8'hFF, 3'b000, status_radar_mode[1:0], 5'b00000, status_stream_ctrl[2:0], status_cfar_threshold[15:0]}
// = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
// = 8'hFF, 5'b00001, 8'b00000101, 16'hABCD
// = FF_09_05_ABCD? Let me compute carefully:
// Bits [31:24] = 8'hFF = 0xFF
// Bits [23:21] = 3'b000
// Bits [20:19] = 2'b01 (mode)
// Bits [18:14] = 5'b00000
// Bits [13:11] = 3'b101 (stream_ctrl)
// Bits [10:0] = ... wait, cfar_threshold is 16 bits → [15:0]
// Total bits = 8+3+2+5+3+16 = 37 bits — won't fit in 32!
// Re-reading the RTL: the packing at line 241 is:
// {8'hFF, 3'b000, status_radar_mode, 5'b00000, status_stream_ctrl, status_cfar_threshold}
// = 8 + 3 + 2 + 5 + 3 + 16 = 37 bits
// This would be truncated to 32 bits. Let me re-read the actual RTL to check.
// For now, just verify status_words[1] (word index 1 in the packet = idx 2 in FSM)
// status_words[1] = {status_long_chirp, status_long_listen} = {16'd3000, 16'd13700}
check(uut.status_words[1] === {16'd3000, 16'd13700},
"Status readback: word 1 = {long_chirp, long_listen}");
check(uut.status_words[2] === {16'd17540, 16'd50},
"Status readback: word 2 = {guard, short_chirp}");
check(uut.status_words[3] === {16'd17450, 10'd0, 6'd32},
"Status readback: word 3 = {short_listen, 0, chirps_per_elev}");
check(uut.status_words[4] === 32'h0000_0000,
"Status readback: word 4 = placeholder 0x00000000");
// ════════════════════════════════════════════════════════
// TEST GROUP 17: New Chirp Timing Opcodes (Gap 2)
// Verify opcodes 0x10-0x15 are properly decoded by the
// read path.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 17: Chirp Timing Opcodes (Gap 2) ---");
apply_reset;
// 0x10: Long chirp cycles
send_host_command({8'h10, 8'h00, 16'd2500});
check(cmd_opcode === 8'h10,
"Chirp opcode: 0x10 (long chirp cycles)");
check(cmd_value === 16'd2500,
"Chirp opcode: value=2500");
// 0x11: Long listen cycles
send_host_command({8'h11, 8'h00, 16'd12000});
check(cmd_opcode === 8'h11,
"Chirp opcode: 0x11 (long listen cycles)");
check(cmd_value === 16'd12000,
"Chirp opcode: value=12000");
// 0x12: Guard cycles
send_host_command({8'h12, 8'h00, 16'd15000});
check(cmd_opcode === 8'h12,
"Chirp opcode: 0x12 (guard cycles)");
check(cmd_value === 16'd15000,
"Chirp opcode: value=15000");
// 0x13: Short chirp cycles
send_host_command({8'h13, 8'h00, 16'd40});
check(cmd_opcode === 8'h13,
"Chirp opcode: 0x13 (short chirp cycles)");
check(cmd_value === 16'd40,
"Chirp opcode: value=40");
// 0x14: Short listen cycles
send_host_command({8'h14, 8'h00, 16'd16000});
check(cmd_opcode === 8'h14,
"Chirp opcode: 0x14 (short listen cycles)");
check(cmd_value === 16'd16000,
"Chirp opcode: value=16000");
// 0x15: Chirps per elevation
send_host_command({8'h15, 8'h00, 16'd16});
check(cmd_opcode === 8'h15,
"Chirp opcode: 0x15 (chirps per elevation)");
check(cmd_value === 16'd16,
"Chirp opcode: value=16");
// 0xFF: Status request (opcode decode check — actual readback tested above)
send_host_command({8'hFF, 8'h00, 16'h0000});
check(cmd_opcode === 8'hFF,
"Chirp opcode: 0xFF (status request)");
// ════════════════════════════════════════════════════════
// Summary
// ════════════════════════════════════════════════════════