FlintyLemming/PLFM_RADAR
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)

Browse Source 
Register map: 0x10-0x15 chirp timing overrides, 0xFF status readback,
0x03 CFAR threshold now wired to actual compare, 0x04 stream control
gates USB write FSM. Status readback sends 7-word packet (0xBB header,
5 status words, 0x55 footer) via toggle CDC.

radar_mode_controller: 6 cfg_* input ports replace hardcoded parameters.
usb_data_interface: stream_control CDC, status_request toggle CDC,
  SEND_STATUS state (3'd7), stream gating in IDLE/HEADER/RANGE/DOPPLER.
radar_system_top: 6 host registers + command decode for 0x10-0x15/0xFF.
radar_receiver_final: 6 host_* timing passthrough ports.

Testbench coverage: RMC 81 checks (+TG16 runtime reconfig), USB 77
checks (+TG15 stream gating, TG16 status readback, TG17 chirp opcodes).
Fixed iverilog 13.0 forward-ref for status_req_toggle_100m.
This commit is contained in:
Jason
2026-03-19 23:54:48 +02:00
parent d2f20f5c15
commit 7cdfa486e5
8 changed files with 604 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/radar_mode_controller.v
+22 -10
View File
@@ -61,6 +61,17 @@ module radar_mode_controller #(
// Single-chirp trigger (active in mode 10)
input wire trigger,
// Gap 2: Runtime-configurable timing inputs from host USB commands.
// When connected, these override the compile-time parameters.
// When left at default (tied to parameter values at instantiation),
// behavior is identical to pre-Gap-2.
input wire [15:0] cfg_long_chirp_cycles,
input wire [15:0] cfg_long_listen_cycles,
input wire [15:0] cfg_guard_cycles,
input wire [15:0] cfg_short_chirp_cycles,
input wire [15:0] cfg_short_listen_cycles,
input wire [5:0] cfg_chirps_per_elev,
// Outputs to receiver processing chain
output reg use_long_chirp,
output reg mc_new_chirp,
@@ -173,8 +184,8 @@ always @(posedge clk or negedge reset_n) begin
mc_new_chirp <= ~mc_new_chirp; // Toggle output
use_long_chirp <= 1'b1; // Default to long chirp
// Track chirp count
if (chirp_count < CHIRPS_PER_ELEVATION - 1)
// Track chirp count (Gap 2: use runtime cfg_chirps_per_elev)
if (chirp_count < cfg_chirps_per_elev - 1)
chirp_count <= chirp_count + 1;
else
chirp_count <= 6'd0;
@@ -226,7 +237,7 @@ always @(posedge clk or negedge reset_n) begin
S_LONG_CHIRP: begin
use_long_chirp <= 1'b1;
if (timer < LONG_CHIRP_CYCLES - 1)
if (timer < cfg_long_chirp_cycles - 1)
timer <= timer + 1;
else begin
timer <= 18'd0;
@@ -235,7 +246,7 @@ always @(posedge clk or negedge reset_n) begin
end
S_LONG_LISTEN: begin
if (timer < LONG_LISTEN_CYCLES - 1)
if (timer < cfg_long_listen_cycles - 1)
timer <= timer + 1;
else begin
timer <= 18'd0;
@@ -244,7 +255,7 @@ always @(posedge clk or negedge reset_n) begin
end
S_GUARD: begin
if (timer < GUARD_CYCLES - 1)
if (timer < cfg_guard_cycles - 1)
timer <= timer + 1;
else begin
timer <= 18'd0;
@@ -255,7 +266,7 @@ always @(posedge clk or negedge reset_n) begin
S_SHORT_CHIRP: begin
use_long_chirp <= 1'b0;
if (timer < SHORT_CHIRP_CYCLES - 1)
if (timer < cfg_short_chirp_cycles - 1)
timer <= timer + 1;
else begin
timer <= 18'd0;
@@ -264,7 +275,7 @@ always @(posedge clk or negedge reset_n) begin
end
S_SHORT_LISTEN: begin
if (timer < SHORT_LISTEN_CYCLES - 1)
if (timer < cfg_short_listen_cycles - 1)
timer <= timer + 1;
else begin
timer <= 18'd0;
@@ -274,7 +285,8 @@ always @(posedge clk or negedge reset_n) begin
S_ADVANCE: begin
// Advance chirp/elevation/azimuth counters
if (chirp_count < CHIRPS_PER_ELEVATION - 1) begin
// (Gap 2: use runtime cfg_chirps_per_elev)
if (chirp_count < cfg_chirps_per_elev - 1) begin
// Next chirp in current elevation
chirp_count <= chirp_count + 1;
mc_new_chirp <= ~mc_new_chirp;
@@ -339,7 +351,7 @@ always @(posedge clk or negedge reset_n) begin
end
S_LONG_CHIRP: begin
if (timer < LONG_CHIRP_CYCLES - 1)
if (timer < cfg_long_chirp_cycles - 1)
timer <= timer + 1;
else begin
timer <= 18'd0;
@@ -348,7 +360,7 @@ always @(posedge clk or negedge reset_n) begin
end
S_LONG_LISTEN: begin
if (timer < LONG_LISTEN_CYCLES - 1)
if (timer < cfg_long_listen_cycles - 1)
timer <= timer + 1;
else begin
// Single chirp done, return to idle