fix(adar1000): populate VM_I/VM_Q phase tables; remove dead VM_GAIN
The ADAR1000 vector-modulator I/Q lookup tables VM_I[128] and VM_Q[128]
were declared but defined as empty initialiser lists since the first
commit (5fbe97f). Every call to adarSetRxPhase / adarSetTxPhase therefore
wrote (I=0x00, Q=0x00) to registers 0x21/0x23 (Rx) and 0x32/0x34 (Tx)
regardless of the requested phase state, leaving beam steering completely
non-functional in firmware.
This commit:
* Populates VM_I[128] and VM_Q[128] from ADAR1000 datasheet Rev. B
Tables 13-16 (p.34) on a uniform 2.8125 deg grid (360 / 128 states).
Byte format: bits[7:6] reserved 0, bit[5] polarity (1 = positive
lobe), bits[4:0] 5-bit unsigned magnitude - exactly as specified.
* Removes VM_GAIN[128] declaration and (empty) definition. The
ADAR1000 has no separate VM gain register; per-channel VGA gain is
set via CHx_RX_GAIN (0x10-0x13) / CHx_TX_GAIN (0x1C-0x1F) by
adarSetRxVgaGain / adarSetTxVgaGain. VM_GAIN was never populated,
never read anywhere in the firmware, and its presence falsely
suggested a missing scaling step in the signal path.
* Adds 9_Firmware/tests/cross_layer/adar1000_vm_reference.py: an
independently-derived ground-truth module containing the full
datasheet table plus byte-format / uniform-grid / quadrant-symmetry
/ cardinal-point invariant checkers and a tolerant C array parser.
* Adds TestTier2Adar1000VmTableGroundTruth (9 tests) to
test_cross_layer_contract.py, including a tokenising C/C++
comment+string stripper used by the VM_GAIN reintroduction guard,
and an adversarial self-test that corrupts one byte and asserts
the comparison detects it (defends against silent bypass via
future fixture/parser refactors).
Adversarially validated: removing the firmware definitions, flipping
a single byte, or reintroducing VM_GAIN as code each cause the suite
to fail; restoring causes it to pass. VM_GAIN appearing inside string
literals or comments correctly does NOT trip the guard.
Closes the empty-table half of the ADAR1000 phase-control bug class.
The separate channel-rotation issue (#90) will be addressed in a
follow-up PR.
Refs: 7_Components Datasheets and Application notes/ADAR1000.pdf
Rev. B Tables 13-16 p.34
This commit is contained in:
Jason
@@ -20,18 +20,71 @@ static const struct {
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{ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin} // ADAR1000 #4
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};
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// Vector Modulator lookup tables
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// ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
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//
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// Source: Analog Devices ADAR1000 datasheet Rev. B, Tables 13-16, page 34
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// (7_Components Datasheets and Application notes/ADAR1000.pdf)
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// Cross-checked against the ADI Linux mainline driver (GPL-2.0, NOT vendored):
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// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/
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// drivers/iio/beamformer/adar1000.c (adar1000_phase_values[])
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// The 128 byte values themselves are factual data from the datasheet and are
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// not subject to copyright; only the ADI driver code is GPL.
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//
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// Byte format (per datasheet):
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// bit [7:6] reserved (0)
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// bit [5] polarity: 1 = positive lobe (sign(I) or sign(Q) >= 0)
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// 0 = negative lobe
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// bits [4:0] 5-bit unsigned magnitude (0..31)
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// At magnitude=0 the polarity bit is physically meaningless; the datasheet
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// uses POL=1 (e.g. VM_Q at 0 deg = 0x20, VM_I at 90 deg = 0x21).
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//
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// Index mapping is uniform: VM_I[k] / VM_Q[k] correspond to phase angle
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// k * 360/128 = k * 2.8125 degrees. Callers index as VM_*[phase % 128].
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const uint8_t ADAR1000Manager::VM_I[128] = {
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// ... (same as in your original file)
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0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D, // [ 0] 0.0000 deg
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0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37, // [ 8] 22.5000 deg
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0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E, // [ 16] 45.0000 deg
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0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22, // [ 24] 67.5000 deg
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0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, // [ 32] 90.0000 deg
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0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14, // [ 40] 112.5000 deg
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0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C, // [ 48] 135.0000 deg
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0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, // [ 56] 157.5000 deg
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0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D, // [ 64] 180.0000 deg
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0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, // [ 72] 202.5000 deg
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0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E, // [ 80] 225.0000 deg
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0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02, // [ 88] 247.5000 deg
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0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, // [ 96] 270.0000 deg
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0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34, // [104] 292.5000 deg
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0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C, // [112] 315.0000 deg
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0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F, // [120] 337.5000 deg
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};
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const uint8_t ADAR1000Manager::VM_Q[128] = {
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// ... (same as in your original file)
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0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, // [ 0] 0.0000 deg
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0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34, // [ 8] 22.5000 deg
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0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, // [ 16] 45.0000 deg
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0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D, // [ 24] 67.5000 deg
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0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C, // [ 32] 90.0000 deg
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0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36, // [ 40] 112.5000 deg
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0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D, // [ 48] 135.0000 deg
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0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21, // [ 56] 157.5000 deg
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0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, // [ 64] 180.0000 deg
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0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14, // [ 72] 202.5000 deg
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0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A, // [ 80] 225.0000 deg
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0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D, // [ 88] 247.5000 deg
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0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, // [ 96] 270.0000 deg
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0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16, // [104] 292.5000 deg
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0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D, // [112] 315.0000 deg
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0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, // [120] 337.5000 deg
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};
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const uint8_t ADAR1000Manager::VM_GAIN[128] = {
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// ... (same as in your original file)
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};
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// NOTE: a VM_GAIN[128] table previously existed here as a placeholder but was
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// never populated and never read. The ADAR1000 vector modulator has no
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// separate gain register: phase-state magnitude is encoded directly in
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// bits [4:0] of the VM_I/VM_Q bytes above. Per-channel VGA gain is a
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// distinct register (CHx_RX_GAIN at 0x10-0x13, CHx_TX_GAIN at 0x1C-0x1F)
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// written with the user-supplied byte directly by adarSetRxVgaGain() /
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// adarSetTxVgaGain(). Do not reintroduce a VM_GAIN[] array.
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ADAR1000Manager::ADAR1000Manager() {
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for (int i = 0; i < 4; ++i) {
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@@ -116,10 +116,12 @@ public:
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bool beam_sweeping_active_ = false;
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uint32_t last_beam_update_time_ = 0;
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// Lookup tables
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static const uint8_t VM_I[128];
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// Vector Modulator lookup tables (see ADAR1000_Manager.cpp for provenance).
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// Indexed as VM_*[phase % 128] on a uniform 2.8125 deg grid.
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// No VM_GAIN[] table exists: VM magnitude is bits [4:0] of the I/Q bytes
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// themselves; per-channel VGA gain uses a separate register.
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static const uint8_t VM_I[128];
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static const uint8_t VM_Q[128];
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static const uint8_t VM_GAIN[128];
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// Named defaults for the ADTR1107 and ADAR1000 power sequence.
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static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
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