Merge pull request #86 from shaun0927/fix/golden-ref-adc-formula
fix(cosim): align golden_reference ADC sign conversion with RTL
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@@ -291,9 +291,12 @@ class Mixer:
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Convert 8-bit unsigned ADC to 18-bit signed.
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Convert 8-bit unsigned ADC to 18-bit signed.
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RTL: adc_signed_w = {1'b0, adc_data, {9{1'b0}}} -
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RTL: adc_signed_w = {1'b0, adc_data, {9{1'b0}}} -
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{1'b0, {8{1'b1}}, {9{1'b0}}} / 2
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{1'b0, {8{1'b1}}, {9{1'b0}}} / 2
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= (adc_data << 9) - (0xFF << 9) / 2
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= (adc_data << 9) - (0xFF << 8) [integer division]
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Verilog '/' binds tighter than '-', so the division applies
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= (adc_data << 9) - 0x7F80
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only to the second concatenation:
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{1'b0, 8'hFF, 9'b0} = 0x1FE00
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0x1FE00 / 2 = 0xFF00 = 65280
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Result: (adc_data << 9) - 0xFF00
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"""
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"""
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adc_data_8bit = adc_data_8bit & 0xFF
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adc_data_8bit = adc_data_8bit & 0xFF
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# {1'b0, adc_data, 9'b0} = adc_data << 9, zero-padded to 18 bits
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# {1'b0, adc_data, 9'b0} = adc_data << 9, zero-padded to 18 bits
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@@ -290,9 +290,9 @@ def run_ddc(adc_samples):
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for n in range(n_samples):
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for n in range(n_samples):
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# ADC sign conversion: RTL does offset binary → signed 18-bit
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# ADC sign conversion: RTL does offset binary → signed 18-bit
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# adc_signed_w = {1'b0, adc_data, 9'b0} - {1'b0, 8'hFF, 9'b0}/2
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# adc_signed_w = {1'b0, adc_data, 9'b0} - {1'b0, 8'hFF, 9'b0}/2
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# Simplified: center around zero, scale to 18-bit
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# Exact: (adc_val << 9) - 0xFF00, where 0xFF00 = {1'b0,8'hFF,9'b0}/2
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adc_val = int(adc_samples[n])
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adc_val = int(adc_samples[n])
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adc_signed = (adc_val - 128) << 9 # Approximate RTL sign conversion to 18-bit
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adc_signed = (adc_val << 9) - 0xFF00 # Exact RTL: {1'b0,adc,9'b0} - {1'b0,8'hFF,9'b0}/2
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adc_signed = saturate(adc_signed, 18)
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adc_signed = saturate(adc_signed, 18)
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# NCO lookup (ignoring dithering for golden reference)
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# NCO lookup (ignoring dithering for golden reference)
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