Fix 6 RTL bugs in FPGA signal processing chain

- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port

All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -11,6 +11,9 @@ module radar_receiver_final (
     input wire adc_dco_n,            // Data Clock Output N (400MHz LVDS)
 	 output wire adc_pwdn,
     
+    // Chirp counter from transmitter (for frame sync and matched filter)
+    input wire [5:0] chirp_counter,
+    
     output reg [31:0] doppler_output,
     output reg doppler_valid,
     output reg [4:0] doppler_bin,
@@ -19,7 +22,7 @@ module radar_receiver_final (
 
 // ========== INTERNAL SIGNALS ==========
 wire use_long_chirp;
-wire [5:0] chirp_counter;
+// NOTE: chirp_counter is now an input port (was undriven internal wire — bug NEW-1)
 wire chirp_start;
 wire azimuth_change;
 wire elevation_change;