Fix 6 RTL bugs in FPGA signal processing chain

- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port

All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -238,8 +238,18 @@ cic_decimator_4x_enhanced cic_q_inst (
     .data_out_valid(cic_valid_q)
 );
 
-assign cic_valid = cic_valid_i & cic_valid_q;
-
+assign cic_valid = cic_valid_i & cic_valid_q;
+
+// ============================================================================
+// Enhanced FIR Filters with FIXED valid signal handling
+// NOTE: Wire declarations moved BEFORE CDC instances to fix forward-reference
+//       error in Icarus Verilog (was originally after CDC instantiation)
+// ============================================================================
+wire fir_in_valid_i, fir_in_valid_q;
+wire fir_valid_i, fir_valid_q;
+wire fir_i_ready, fir_q_ready;
+wire [17:0] fir_d_in_i, fir_d_in_q; 
+
 cdc_adc_to_processing #(
     .WIDTH(18),
     .STAGES(3)
@@ -266,14 +276,10 @@ cdc_adc_to_processing #(
     .dst_valid(fir_in_valid_q)
 );
 
-// ============================================================================
-// Enhanced FIR Filters with FIXED valid signal handling
-// ============================================================================
-wire fir_in_valid_i, fir_in_valid_q;
-wire fir_valid_i, fir_valid_q;
-wire fir_i_ready, fir_q_ready;
-wire [17:0] fir_d_in_i, fir_d_in_q; 
-
+// ============================================================================
+// FIR Filter Instances
+// ============================================================================
+
 // FIR I channel
 fir_lowpass_parallel_enhanced fir_i_inst (
     .clk(clk_100m),