docs: update constraints README with USB_MODE architecture and build guide
Add USB Interface Architecture section documenting the USB_MODE parameter, generate block mechanism, per-target wrapper pattern, FT2232H pin map, and build quick-reference. Update top modules table (50T now uses radar_system_top_50t), bank voltage tables, and signal differences to reflect the FT2232H/FT601 dual-interface design.
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Jason
@@ -4,19 +4,19 @@
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| File | Device | Package | Purpose |
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|------|--------|---------|---------|
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| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | Upstream author's board (copy of `cntrt.xdc`) |
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| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Production board (new PCB design) |
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| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | 50T production board |
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| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | 200T premium dev board |
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| `te0712_te0701_minimal.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Trenz dev split target (minimal clock/reset + LEDs/status) |
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| `te0713_te0701_minimal.xdc` | XC7A200T-2FBG484C | FBG484 (484-ball BGA) | Trenz alternate SoM target (minimal clock + FMC status outputs) |
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## Why Four Files
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The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production
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AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources.
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The two devices have completely different packages and pin names, so each needs its
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own constraint file.
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The 50T production board uses an XC7A50T in an FTG256 package. The 200T premium
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dev board uses an XC7A200T for more logic, BRAM, and DSP resources. The two
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devices have completely different packages and pin names, so each needs its own
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constraint file.
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The Trenz TE0712/TE0701 path uses the same FPGA part as production but different board
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The Trenz TE0712/TE0701 path uses the same FPGA part as the 200T but different board
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pinout and peripherals. The dev target is split into its own top wrapper
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(`radar_system_top_te0712_dev.v`) and minimal constraints file to avoid accidental mixing
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of production pin assignments during bring-up.
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@@ -25,9 +25,83 @@ The Trenz TE0713/TE0701 path supports situations where TE0712 lead time is prohi
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TE0713 uses XC7A200T-2FBG484C (commercial temp grade) and requires separate clock mapping,
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so it has its own dev top and XDC.
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## USB Interface Architecture (USB_MODE)
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The radar system supports two USB data interfaces, selected at **compile time** via
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the `USB_MODE` parameter in `radar_system_top.v`:
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| USB_MODE | Interface | Bus Width | Speed | Board Target |
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|----------|-----------|-----------|-------|--------------|
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| 0 (default) | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
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| 1 | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
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### How USB_MODE Works
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`radar_system_top.v` contains a Verilog `generate` block that instantiates exactly
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one USB interface module based on the `USB_MODE` parameter:
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```
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generate
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if (USB_MODE == 0) begin : gen_ft601
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usb_data_interface usb_inst (...) // FT601, 32-bit
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// FT2232H ports tied off to inactive
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end else begin : gen_ft2232h
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usb_data_interface_ft2232h usb_inst (...) // FT2232H, 8-bit
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// FT601 ports tied off to inactive
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end
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endgenerate
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```
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Both interfaces share the same internal radar data bus and host command interface.
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The unused interface's I/O pins are tied to safe inactive states (active-low
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signals high, active-high signals low, bidirectional buses high-Z).
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### How USB_MODE Is Passed Per Board Target
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The parameter is set via a **wrapper module** that overrides the default:
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- **50T production**: `radar_system_top_50t.v` instantiates the core with
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`.USB_MODE(1)` and maps the FT2232H's 60 MHz `CLKOUT` to the shared
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`ft601_clk_in` port. FT601 inputs are tied inactive; outputs go to `_nc` wires.
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```verilog
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// In radar_system_top_50t.v:
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radar_system_top #(
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.USB_MODE(1)
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) u_core ( ... );
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```
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- **200T dev board**: `radar_system_top` is used directly as the top module.
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`USB_MODE` defaults to `0` (FT601). No wrapper needed.
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### RTL Files by USB Interface
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| File | Purpose |
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|------|---------|
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| `usb_data_interface.v` | FT601 USB 3.0 module (32-bit, USB_MODE=0) |
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| `usb_data_interface_ft2232h.v` | FT2232H USB 2.0 module (8-bit, USB_MODE=1) |
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| `radar_system_top.v` | Core module with USB_MODE generate block |
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| `radar_system_top_50t.v` | 50T wrapper: sets USB_MODE=1, ties off FT601 |
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### FT2232H Pin Map (50T, Bank 35, VCCO=3.3V)
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All connections are direct between U6 (FT2232HQ) and U42 (XC7A50T). Only
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Channel A is used (245 Synchronous FIFO mode). Channel B is unconnected.
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| Signal | FT2232H Pin | FPGA Ball | Direction |
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|--------|-------------|-----------|-----------|
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| FT_D[7:0] | ADBUS[7:0] | K1,J3,H3,G4,F2,D1,C3,C1 | Bidirectional |
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| FT_RXF# | ACBUS0 | A2 | Input (FIFO not empty) |
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| FT_TXE# | ACBUS1 | B2 | Input (FIFO not full) |
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| FT_RD# | ACBUS2 | A3 | Output (read strobe) |
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| FT_WR# | ACBUS3 | A4 | Output (write strobe) |
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| FT_SIWUA | ACBUS4 | A5 | Output (send immediate) |
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| FT_CLKOUT | ACBUS5 | C4 (MRCC) | Input (60 MHz clock) |
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| FT_OE# | ACBUS6 | B7 | Output (bus direction) |
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## Bank Voltage Assignments
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### XC7A50T-FTG256 (Upstream)
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### XC7A50T-FTG256 (50T Production)
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| Bank | VCCO | Signals |
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|------|------|---------|
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@@ -35,9 +109,9 @@ so it has its own dev top and XDC.
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| 14 | 3.3V | ADC LVDS (LVDS_33), SPI flash |
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| 15 | 3.3V | DAC, clocks, STM32 3.3V SPI, DIG bus |
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| 34 | 1.8V | ADAR1000 control, SPI 1.8V side |
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| 35 | 3.3V | Unused (no signal connections) |
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| 35 | 3.3V | FT2232H USB 2.0 (8-bit data + control, 15 signals) |
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### XC7A200T-FBG484 (Production)
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### XC7A200T-FBG484 (200T Premium Dev Board)
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| Bank | VCCO | Used/Avail | Signals |
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|------|------|------------|---------|
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@@ -50,15 +124,46 @@ so it has its own dev top and XDC.
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## Signal Differences Between Targets
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| Signal | Upstream (FTG256) | Production (FBG484) |
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|--------|-------------------|---------------------|
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| FT601 USB | Unwired (chip placed, no nets) | Fully wired, Bank 16 |
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| Signal | 50T Production (FTG256) | 200T Dev (FBG484) |
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|--------|-------------------------|-------------------|
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| USB interface | FT2232H USB 2.0 (8-bit, Bank 35) | FT601 USB 3.0 (32-bit, Bank 16) |
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| USB_MODE | 1 (via `radar_system_top_50t` wrapper) | 0 (default in `radar_system_top`) |
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| USB clock | 60 MHz from FT2232H CLKOUT | 100 MHz from FT601 |
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| `dac_clk` | Not connected (DAC clocked by AD9523 directly) | Routed, FPGA drives DAC |
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| `ft601_be` width | `[1:0]` in upstream RTL | `[3:0]` (RTL updated) |
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| `ft601_be` width | N/A (FT601 unused, tied off) | `[3:0]` (RTL updated) |
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| ADC LVDS standard | LVDS_33 (3.3V bank) | LVDS_25 (2.5V bank, better quality) |
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| Status/debug outputs | No physical pins (commented out) | All routed to Banks 35 + 13 |
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## How to Select in Vivado
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## How to Build
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### Quick Reference
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```bash
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# SSH into the build server:
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ssh -i ~/.ssh/gpu_server_key -p 8765 -o StrictHostKeyChecking=no jason-stone@livepeerservice.ddns.net
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source /mnt/bcache/Xilinx/Vivado/2025.2/Vivado/settings64.sh
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cd /home/jason-stone/PLFM_RADAR_work/9_Firmware/9_2_FPGA
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# 50T production build (FT2232H, USB_MODE=1):
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vivado -mode batch -source scripts/50t/build_50t.tcl 2>&1 | tee build_50t/vivado.log
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# 200T dev build (FT601, USB_MODE=0):
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vivado -mode batch -source scripts/200t/build_200t.tcl \
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-log build/build.log -journal build/build.jou
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```
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The build scripts automatically select the correct top module and constraints:
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| Build Script | Top Module | Constraints | USB_MODE |
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|--------------|------------|-------------|----------|
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| `scripts/50t/build_50t.tcl` | `radar_system_top_50t` | `xc7a50t_ftg256.xdc` | 1 (FT2232H) |
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| `scripts/200t/build_200t.tcl` | `radar_system_top` | `xc7a200t_fbg484.xdc` | 0 (FT601) |
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You do NOT need to set `USB_MODE` manually. The top module selection handles it:
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- `radar_system_top_50t` forces `USB_MODE=1` internally
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- `radar_system_top` defaults to `USB_MODE=0`
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## How to Select Constraints in Vivado
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In the Vivado project, only one target XDC should be active at a time:
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@@ -85,12 +190,12 @@ read_xdc constraints/te0713_te0701_minimal.xdc
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## Top Modules by Target
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| Target | Top module | Notes |
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|--------|------------|-------|
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| Upstream FTG256 | `radar_system_top` | Legacy board support |
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| Production FBG484 | `radar_system_top` | Main AERIS-10 board |
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| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | Minimal bring-up wrapper while pinout/peripherals are migrated |
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| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | Alternate SoM wrapper (TE0713 clock mapping) |
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| Target | Top module | USB_MODE | USB Interface | Notes |
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|--------|------------|----------|---------------|-------|
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| 50T Production (FTG256) | `radar_system_top_50t` | 1 | FT2232H (8-bit) | Wrapper sets USB_MODE=1, ties off FT601 |
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| 200T Dev (FBG484) | `radar_system_top` | 0 (default) | FT601 (32-bit) | No wrapper needed |
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| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (default) | FT601 (32-bit) | Minimal bring-up wrapper |
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| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (default) | FT601 (32-bit) | Alternate SoM wrapper |
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## Trenz Split Status
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@@ -142,11 +247,19 @@ TE0713 outputs:
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## Notes
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- The production XDC pin assignments are **recommended** for the new PCB.
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- **USB_MODE is compile-time only.** You cannot switch USB interfaces at runtime.
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Each board target has exactly one USB chip physically connected.
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- The 50T production build must use `radar_system_top_50t` as top module. Using
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`radar_system_top` directly will default to FT601 (USB_MODE=0), which has no
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physical connection on the 50T board.
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- The 200T XDC pin assignments are **recommended** for the new PCB.
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The PCB designer should follow this allocation.
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- Bank 16 (FT601) is fully utilized at 50/50 pins. No room for expansion
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- Bank 16 on the 200T (FT601) is fully utilized at 50/50 pins. No room for expansion
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on that bank.
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- Bank 35 (status/debug) is also at capacity (50/50). Additional debug
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- Bank 35 on the 200T (status/debug) is also at capacity (50/50). Additional debug
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signals should use Bank 13 spare pins (18 remaining).
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- Bank 35 on the 50T is used for FT2232H (15 signals). Remaining pins are available
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for future expansion.
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- Clock inputs are placed on MRCC (Multi-Region Clock Capable) pins to
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ensure proper clock tree access.
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ensure proper clock tree access. The FT2232H CLKOUT (60 MHz) is on
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pin C4 (`IO_L12N_T1_MRCC_35`).
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