fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H
Replace direct !reset_n async sense with a registered active-high reset_h (max_fanout=50) in nco_400m_enhanced, cic_decimator_4x_enhanced, and ddc_400m. The prior single-LUT1 / 700+ load net was the root cause of WNS=-0.626 ns in the 400 MHz clock domain on the xc7a50t build. Vivado replicates the constrained register into ≈14 regional copies, each driving ≤50 loads, closing timing at 2.5 ns. Change radar_system_top default USB_MODE from 0 (FT601) to 1 (FT2232H). FT601 remains available for the 200T premium board via explicit parameter override; the 50T production wrapper already hard-codes USB_MODE=1. Regression: add usb_data_interface_ft2232h.v to PROD_RTL lint list and both system-top TB compile commands; fix legacy radar_system_tb hierarchical probe from gen_ft601.usb_inst to gen_ft2232h.usb_inst. Golden reference files (rtl_bb_dc.csv, rx_final_doppler_out.csv, golden_doppler.mem) regenerated to reflect the +1-cycle registered-reset boundary behaviour; Receiver golden-compare passes 18/18 checks. All 25 regression tests pass (0 failures, 0 skipped).
This commit is contained in:
Jason
+346
-328
@@ -1,106 +1,66 @@
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`timescale 1ns / 1ps
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module ddc_400m_enhanced (
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input wire clk_400m, // 400MHz clock from ADC DCO
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input wire clk_100m, // 100MHz system clock
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input wire reset_n,
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input wire mixers_enable,
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input wire [7:0] adc_data, // ADC data at 400MHz
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`timescale 1ns / 1ps
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module ddc_400m_enhanced (
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input wire clk_400m, // 400MHz clock from ADC DCO
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input wire clk_100m, // 100MHz system clock
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input wire reset_n,
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input wire mixers_enable,
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input wire [7:0] adc_data, // ADC data at 400MHz
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input wire adc_data_valid_i, // Valid at 400MHz
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input wire adc_data_valid_q,
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output wire signed [17:0] baseband_i,
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output wire signed [17:0] baseband_q,
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input wire adc_data_valid_q,
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output wire signed [17:0] baseband_i,
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output wire signed [17:0] baseband_q,
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output wire baseband_valid_i,
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output wire baseband_valid_q,
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output wire [1:0] ddc_status,
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// Enhanced interfaces
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output wire [7:0] ddc_diagnostics,
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output wire baseband_valid_q,
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output wire [1:0] ddc_status,
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// Enhanced interfaces
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output wire [7:0] ddc_diagnostics,
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output wire mixer_saturation,
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output wire filter_overflow,
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input wire [1:0] test_mode,
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input wire [15:0] test_phase_inc,
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input wire force_saturation,
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input wire reset_monitors,
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output wire [31:0] debug_sample_count,
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output wire [17:0] debug_internal_i,
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output wire [17:0] debug_internal_q
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);
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// Parameters for numerical precision
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parameter ADC_WIDTH = 8;
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parameter NCO_WIDTH = 16;
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parameter MIXER_WIDTH = 18;
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parameter OUTPUT_WIDTH = 18;
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// IF frequency parameters
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parameter IF_FREQ = 120000000;
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parameter FS = 400000000;
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parameter PHASE_WIDTH = 32;
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// Internal signals
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wire signed [15:0] sin_out, cos_out;
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wire nco_ready;
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wire cic_valid;
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wire fir_valid;
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wire [17:0] cic_i_out, cic_q_out;
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wire signed [17:0] fir_i_out, fir_q_out;
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input wire [1:0] test_mode,
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input wire [15:0] test_phase_inc,
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input wire force_saturation,
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input wire reset_monitors,
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output wire [31:0] debug_sample_count,
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output wire [17:0] debug_internal_i,
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output wire [17:0] debug_internal_q
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);
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// Parameters for numerical precision
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parameter ADC_WIDTH = 8;
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parameter NCO_WIDTH = 16;
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parameter MIXER_WIDTH = 18;
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parameter OUTPUT_WIDTH = 18;
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// IF frequency parameters
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parameter IF_FREQ = 120000000;
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parameter FS = 400000000;
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parameter PHASE_WIDTH = 32;
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// Internal signals
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wire signed [15:0] sin_out, cos_out;
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wire nco_ready;
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wire cic_valid;
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wire fir_valid;
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wire [17:0] cic_i_out, cic_q_out;
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wire signed [17:0] fir_i_out, fir_q_out;
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// Diagnostic registers
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reg [2:0] saturation_count;
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reg overflow_detected;
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reg [7:0] error_counter;
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// ============================================================================
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// 400 MHz Reset Synchronizer
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//
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// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
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// Using it directly as an async reset in the 400 MHz domain causes the reset
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// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
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// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
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// domain, requiring 18.243ns of routing (WNS = -18.081ns).
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//
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// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
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// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
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// path from reset_n to all 400 MHz registers). Reset deassertion is
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// synchronized to clk_400m rising edge, preventing metastability.
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//
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// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
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// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
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// (already synchronized to 100 MHz at radar_system_top level).
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// ============================================================================
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
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(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
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// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
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(* max_fanout = 50 *) reg reset_400m;
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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reset_sync_400m <= 2'b00;
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reset_400m <= 1'b1;
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end else begin
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reset_sync_400m <= {reset_sync_400m[0], 1'b1};
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reset_400m <= ~reset_sync_400m[1];
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end
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end
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// CDC synchronization for control signals (2-stage synchronizers)
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(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
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(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
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wire mixers_enable_sync;
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wire force_saturation_sync;
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// Debug monitoring signals
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reg [31:0] sample_counter;
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wire signed [17:0] debug_mixed_i_trunc;
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wire signed [17:0] debug_mixed_q_trunc;
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// Real-time status monitoring
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reg [7:0] signal_power_i, signal_power_q;
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reg [7:0] signal_power_i, signal_power_q;
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// Internal mixing signals
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// Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
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// The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
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@@ -118,61 +78,112 @@ reg [4:0] dsp_valid_pipe;
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// Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
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// This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
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// ensuring WNS > 0 at 400 MHz regardless of placement seed
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(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
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// Output stage registers
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reg signed [17:0] baseband_i_reg, baseband_q_reg;
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reg baseband_valid_reg;
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// ============================================================================
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(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
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// Output stage registers
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reg signed [17:0] baseband_i_reg, baseband_q_reg;
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reg baseband_valid_reg;
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// ============================================================================
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// Phase Dithering Signals
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// ============================================================================
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wire [7:0] phase_dither_bits;
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reg [31:0] phase_inc_dithered;
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// ============================================================================
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// Debug Signal Assignments
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// ============================================================================
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assign debug_internal_i = mixed_i[25:8];
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assign debug_internal_q = mixed_q[25:8];
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assign debug_sample_count = sample_counter;
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assign debug_mixed_i_trunc = mixed_i[25:8];
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assign debug_mixed_q_trunc = mixed_q[25:8];
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// ============================================================================
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// Clock Domain Crossing for Control Signals (2-stage synchronizers)
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reg [31:0] phase_inc_dithered;
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// ============================================================================
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// Debug Signal Assignments
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// ============================================================================
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assign debug_internal_i = mixed_i[25:8];
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assign debug_internal_q = mixed_q[25:8];
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assign debug_sample_count = sample_counter;
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assign debug_mixed_i_trunc = mixed_i[25:8];
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assign debug_mixed_q_trunc = mixed_q[25:8];
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// ============================================================================
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// 400 MHz Reset Synchronizer
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//
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// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
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// Using it directly as an async reset in the 400 MHz domain causes the reset
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// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
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// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
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// domain, requiring 18.243ns of routing (WNS = -18.081ns).
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//
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// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
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// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
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// path from reset_n to all 400 MHz registers). Reset deassertion is
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//
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// reset_400m : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
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// This is THE signal fed to every synchronous 400 MHz FDRE
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// and every DSP48E1 RST pin in this module and its children
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// (NCO, CIC, LFSR). Vivado replicates the register (~14
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// copies) so each replica drives ≈50 loads regionally,
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// eliminating the single-LUT1 / 702-load net that caused
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// WNS=-0.626 ns in Build N.
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//
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// System-level invariants preserved:
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// I1 Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
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// (2 sync + 1 replicated-reg fanout). At 400 MHz = 7.5 ns << any
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// system-level reset assertion duration.
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// I2 Reset de-assertion is always synchronous to clk_400m (via
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// reset_sync_400m), never glitches.
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// I3 DSP48E1 RST pins are all fed from Q of a register — glitch-free.
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// I4 No new CDC introduced: reset_400m is entirely in clk_400m domain.
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// I5 Power-up: reset_n is asserted externally and mmcm_locked is low;
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// reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
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// FDREs stay cleared. Safe.
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// ============================================================================
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
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(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
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// Active-high replicated reset for all synchronous 400 MHz consumers
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(* max_fanout = 50 *) reg reset_400m = 1'b1;
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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reset_sync_400m <= 2'b00;
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reset_400m <= 1'b1;
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end else begin
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reset_sync_400m <= {reset_sync_400m[0], 1'b1};
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reset_400m <= ~reset_sync_400m[1];
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end
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end
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// CDC synchronization for control signals (2-stage synchronizers)
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(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
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(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
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wire mixers_enable_sync;
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wire force_saturation_sync;
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assign mixers_enable_sync = mixers_enable_sync_chain[1];
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assign force_saturation_sync = force_saturation_sync_chain[1];
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
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// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
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always @(posedge clk_400m) begin
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if (reset_400m) begin
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mixers_enable_sync_chain <= 2'b00;
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force_saturation_sync_chain <= 2'b00;
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end else begin
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mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
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force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
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end
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end
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// ============================================================================
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// Sample Counter and Debug Monitoring
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m || reset_monitors) begin
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end
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// ============================================================================
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// Sample Counter and Debug Monitoring
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// ============================================================================
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always @(posedge clk_400m) begin
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if (reset_400m || reset_monitors) begin
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sample_counter <= 0;
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error_counter <= 0;
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end else if (adc_data_valid_i && adc_data_valid_q ) begin
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sample_counter <= sample_counter + 1;
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end
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end
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// ============================================================================
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// Enhanced Phase Dithering Instance
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// ============================================================================
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error_counter <= 0;
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end else if (adc_data_valid_i && adc_data_valid_q ) begin
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sample_counter <= sample_counter + 1;
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end
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end
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// ============================================================================
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// Enhanced Phase Dithering Instance
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// ============================================================================
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lfsr_dither_enhanced #(
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.DITHER_WIDTH(8)
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) phase_dither_gen (
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@@ -180,36 +191,36 @@ lfsr_dither_enhanced #(
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.reset_n(reset_n_400m),
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.enable(nco_ready),
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.dither_out(phase_dither_bits)
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);
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// ============================================================================
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// Phase Increment Calculation with Dithering
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// ============================================================================
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// Calculate phase increment for 120MHz IF at 400MHz sampling
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localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
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);
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// ============================================================================
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// Phase Increment Calculation with Dithering
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// ============================================================================
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// Calculate phase increment for 120MHz IF at 400MHz sampling
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localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
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// Apply dithering to reduce spurious tones (registered for 400 MHz timing)
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m)
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always @(posedge clk_400m) begin
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if (reset_400m)
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phase_inc_dithered <= PHASE_INC_120MHZ;
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else
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phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
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end
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// ============================================================================
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// Enhanced NCO with Diagnostics
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// ============================================================================
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end
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// ============================================================================
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// Enhanced NCO with Diagnostics
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// ============================================================================
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nco_400m_enhanced nco_core (
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.clk_400m(clk_400m),
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.reset_n(reset_n_400m),
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.frequency_tuning_word(phase_inc_dithered),
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.phase_valid(mixers_enable),
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.phase_offset(16'h0000),
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.sin_out(sin_out),
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.cos_out(cos_out),
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.dds_ready(nco_ready)
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);
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.reset_n(reset_n_400m),
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.frequency_tuning_word(phase_inc_dithered),
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.phase_valid(mixers_enable),
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.phase_offset(16'h0000),
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.sin_out(sin_out),
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.cos_out(cos_out),
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.dds_ready(nco_ready)
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);
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// ============================================================================
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// Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
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//
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@@ -229,8 +240,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
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{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
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// Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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always @(posedge clk_400m) begin
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if (reset_400m) begin
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dsp_valid_pipe <= 5'b00000;
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end else begin
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dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
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@@ -246,8 +257,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Mod
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reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
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// Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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always @(posedge clk_400m) begin
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if (reset_400m) begin
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cos_nco_pipe <= 0;
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sin_nco_pipe <= 0;
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end else begin
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@@ -257,8 +268,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
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end
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// Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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always @(posedge clk_400m) begin
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if (reset_400m) begin
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adc_signed_reg <= 0;
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cos_pipe_reg <= 0;
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sin_pipe_reg <= 0;
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@@ -270,8 +281,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
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end
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// Stage 2: MREG equivalent
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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always @(posedge clk_400m) begin
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if (reset_400m) begin
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mult_i_internal <= 0;
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mult_q_internal <= 0;
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end else begin
|
||||
@@ -281,8 +292,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
end
|
||||
|
||||
// Stage 3: PREG equivalent
|
||||
always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
if (!reset_n_400m) begin
|
||||
always @(posedge clk_400m) begin
|
||||
if (reset_400m) begin
|
||||
mult_i_reg <= 0;
|
||||
mult_q_reg <= 0;
|
||||
end else begin
|
||||
@@ -292,8 +303,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
end
|
||||
|
||||
// Stage 4: Post-DSP retiming register (matches synthesis path)
|
||||
always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
if (!reset_n_400m) begin
|
||||
always @(posedge clk_400m) begin
|
||||
if (reset_400m) begin
|
||||
mult_i_retimed <= 0;
|
||||
mult_q_retimed <= 0;
|
||||
end else begin
|
||||
@@ -311,8 +322,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
|
||||
// (1.505ns routing observed in Build 26). These fabric registers are placed
|
||||
// near the DSP by the placer, splitting the route into two shorter segments.
|
||||
// DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
|
||||
always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
if (!reset_n_400m) begin
|
||||
always @(posedge clk_400m) begin
|
||||
if (reset_400m) begin
|
||||
cos_nco_pipe <= 0;
|
||||
sin_nco_pipe <= 0;
|
||||
end else begin
|
||||
@@ -329,11 +340,10 @@ DSP48E1 #(
|
||||
.USE_DPORT("FALSE"),
|
||||
.USE_MULT("MULTIPLY"),
|
||||
.USE_SIMD("ONE48"),
|
||||
// Pipeline register attributes — all enabled for max timing
|
||||
.AREG(1),
|
||||
.BREG(1),
|
||||
.MREG(1),
|
||||
.PREG(1), // P register enabled — absorbs CLK→P delay for timing closure
|
||||
.PREG(1),
|
||||
.ADREG(0),
|
||||
.ACASCREG(1),
|
||||
.BCASCREG(1),
|
||||
@@ -344,7 +354,6 @@ DSP48E1 #(
|
||||
.DREG(0),
|
||||
.INMODEREG(0),
|
||||
.OPMODEREG(0),
|
||||
// Pattern detector (unused)
|
||||
.AUTORESET_PATDET("NO_RESET"),
|
||||
.MASK(48'h3fffffffffff),
|
||||
.PATTERN(48'h000000000000),
|
||||
@@ -496,8 +505,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
|
||||
// Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
|
||||
// Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
|
||||
// the 2.500ns clock period at slow process corner
|
||||
always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
if (!reset_n_400m) begin
|
||||
always @(posedge clk_400m) begin
|
||||
if (reset_400m) begin
|
||||
mult_i_retimed <= 0;
|
||||
mult_q_retimed <= 0;
|
||||
end else begin
|
||||
@@ -513,8 +522,8 @@ end
|
||||
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
|
||||
// polluting the critical input path with extra logic
|
||||
// ============================================================================
|
||||
always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
if (!reset_n_400m) begin
|
||||
always @(posedge clk_400m) begin
|
||||
if (reset_400m) begin
|
||||
mixed_i <= 0;
|
||||
mixed_q <= 0;
|
||||
mixed_valid <= 0;
|
||||
@@ -556,31 +565,31 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
|
||||
mixer_overflow_q <= 0;
|
||||
overflow_detected <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced CIC Decimators
|
||||
// ============================================================================
|
||||
wire cic_valid_i, cic_valid_q;
|
||||
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced CIC Decimators
|
||||
// ============================================================================
|
||||
wire cic_valid_i, cic_valid_q;
|
||||
|
||||
cic_decimator_4x_enhanced cic_i_inst (
|
||||
.clk(clk_400m),
|
||||
.reset_n(reset_n_400m),
|
||||
.data_in(mixed_i[33:16]),
|
||||
.data_valid(mixed_valid),
|
||||
.data_out(cic_i_out),
|
||||
.data_out_valid(cic_valid_i)
|
||||
);
|
||||
|
||||
.reset_n(reset_n_400m),
|
||||
.data_in(mixed_i[33:16]),
|
||||
.data_valid(mixed_valid),
|
||||
.data_out(cic_i_out),
|
||||
.data_out_valid(cic_valid_i)
|
||||
);
|
||||
|
||||
cic_decimator_4x_enhanced cic_q_inst (
|
||||
.clk(clk_400m),
|
||||
.reset_n(reset_n_400m),
|
||||
.data_in(mixed_q[33:16]),
|
||||
.data_valid(mixed_valid),
|
||||
.data_out(cic_q_out),
|
||||
.data_out_valid(cic_valid_q)
|
||||
);
|
||||
|
||||
.reset_n(reset_n_400m),
|
||||
.data_in(mixed_q[33:16]),
|
||||
.data_valid(mixed_valid),
|
||||
.data_out(cic_q_out),
|
||||
.data_out_valid(cic_valid_q)
|
||||
);
|
||||
|
||||
assign cic_valid = cic_valid_i & cic_valid_q;
|
||||
|
||||
// ============================================================================
|
||||
@@ -593,96 +602,96 @@ wire fir_valid_i, fir_valid_q;
|
||||
wire fir_i_ready, fir_q_ready;
|
||||
wire [17:0] fir_d_in_i, fir_d_in_q;
|
||||
|
||||
cdc_adc_to_processing #(
|
||||
.WIDTH(18),
|
||||
.STAGES(3)
|
||||
cdc_adc_to_processing #(
|
||||
.WIDTH(18),
|
||||
.STAGES(3)
|
||||
)CDC_FIR_i(
|
||||
.src_clk(clk_400m),
|
||||
.dst_clk(clk_100m),
|
||||
.src_reset_n(reset_n_400m),
|
||||
.dst_reset_n(reset_n),
|
||||
.src_data(cic_i_out),
|
||||
.src_valid(cic_valid_i),
|
||||
.dst_data(fir_d_in_i),
|
||||
.dst_valid(fir_in_valid_i)
|
||||
.dst_reset_n(reset_n),
|
||||
.src_data(cic_i_out),
|
||||
.src_valid(cic_valid_i),
|
||||
.dst_data(fir_d_in_i),
|
||||
.dst_valid(fir_in_valid_i)
|
||||
);
|
||||
|
||||
cdc_adc_to_processing #(
|
||||
.WIDTH(18),
|
||||
.STAGES(3)
|
||||
cdc_adc_to_processing #(
|
||||
.WIDTH(18),
|
||||
.STAGES(3)
|
||||
)CDC_FIR_q(
|
||||
.src_clk(clk_400m),
|
||||
.dst_clk(clk_100m),
|
||||
.src_reset_n(reset_n_400m),
|
||||
.dst_reset_n(reset_n),
|
||||
.src_data(cic_q_out),
|
||||
.src_valid(cic_valid_q),
|
||||
.dst_data(fir_d_in_q),
|
||||
.dst_valid(fir_in_valid_q)
|
||||
);
|
||||
|
||||
.dst_reset_n(reset_n),
|
||||
.src_data(cic_q_out),
|
||||
.src_valid(cic_valid_q),
|
||||
.dst_data(fir_d_in_q),
|
||||
.dst_valid(fir_in_valid_q)
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
// FIR Filter Instances
|
||||
// ============================================================================
|
||||
|
||||
// FIR I channel
|
||||
fir_lowpass_parallel_enhanced fir_i_inst (
|
||||
.clk(clk_100m),
|
||||
.reset_n(reset_n),
|
||||
.data_in(fir_d_in_i), // Use synchronized data
|
||||
.data_valid(fir_in_valid_i), // Use synchronized valid
|
||||
.data_out(fir_i_out),
|
||||
.data_out_valid(fir_valid_i),
|
||||
.fir_ready(fir_i_ready),
|
||||
.filter_overflow()
|
||||
);
|
||||
|
||||
// FIR Q channel
|
||||
fir_lowpass_parallel_enhanced fir_q_inst (
|
||||
.clk(clk_100m),
|
||||
.reset_n(reset_n),
|
||||
.data_in(fir_d_in_q), // Use synchronized data
|
||||
.data_valid(fir_in_valid_q), // Use synchronized valid
|
||||
.data_out(fir_q_out),
|
||||
.data_out_valid(fir_valid_q),
|
||||
.fir_ready(fir_q_ready),
|
||||
.filter_overflow()
|
||||
);
|
||||
|
||||
assign fir_valid = fir_valid_i & fir_valid_q;
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Output Stage
|
||||
// ============================================================================
|
||||
always @(posedge clk_100m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
baseband_i_reg <= 0;
|
||||
baseband_q_reg <= 0;
|
||||
baseband_valid_reg <= 0;
|
||||
end else if (fir_valid) begin
|
||||
baseband_i_reg <= fir_i_out;
|
||||
baseband_q_reg <= fir_q_out;
|
||||
baseband_valid_reg <= 1;
|
||||
end else begin
|
||||
baseband_valid_reg <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ============================================================================
|
||||
// Output Assignments
|
||||
// ============================================================================
|
||||
assign baseband_i = baseband_i_reg;
|
||||
assign baseband_q = baseband_q_reg;
|
||||
// FIR I channel
|
||||
fir_lowpass_parallel_enhanced fir_i_inst (
|
||||
.clk(clk_100m),
|
||||
.reset_n(reset_n),
|
||||
.data_in(fir_d_in_i), // Use synchronized data
|
||||
.data_valid(fir_in_valid_i), // Use synchronized valid
|
||||
.data_out(fir_i_out),
|
||||
.data_out_valid(fir_valid_i),
|
||||
.fir_ready(fir_i_ready),
|
||||
.filter_overflow()
|
||||
);
|
||||
|
||||
// FIR Q channel
|
||||
fir_lowpass_parallel_enhanced fir_q_inst (
|
||||
.clk(clk_100m),
|
||||
.reset_n(reset_n),
|
||||
.data_in(fir_d_in_q), // Use synchronized data
|
||||
.data_valid(fir_in_valid_q), // Use synchronized valid
|
||||
.data_out(fir_q_out),
|
||||
.data_out_valid(fir_valid_q),
|
||||
.fir_ready(fir_q_ready),
|
||||
.filter_overflow()
|
||||
);
|
||||
|
||||
assign fir_valid = fir_valid_i & fir_valid_q;
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Output Stage
|
||||
// ============================================================================
|
||||
always @(posedge clk_100m or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
baseband_i_reg <= 0;
|
||||
baseband_q_reg <= 0;
|
||||
baseband_valid_reg <= 0;
|
||||
end else if (fir_valid) begin
|
||||
baseband_i_reg <= fir_i_out;
|
||||
baseband_q_reg <= fir_q_out;
|
||||
baseband_valid_reg <= 1;
|
||||
end else begin
|
||||
baseband_valid_reg <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ============================================================================
|
||||
// Output Assignments
|
||||
// ============================================================================
|
||||
assign baseband_i = baseband_i_reg;
|
||||
assign baseband_q = baseband_q_reg;
|
||||
assign baseband_valid_i = baseband_valid_reg;
|
||||
assign baseband_valid_q = baseband_valid_reg;
|
||||
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
|
||||
assign mixer_saturation = overflow_detected;
|
||||
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Debug and Monitoring
|
||||
// ============================================================================
|
||||
assign baseband_valid_q = baseband_valid_reg;
|
||||
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
|
||||
assign mixer_saturation = overflow_detected;
|
||||
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Debug and Monitoring
|
||||
// ============================================================================
|
||||
reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
|
||||
|
||||
`ifdef SIMULATION
|
||||
@@ -699,10 +708,10 @@ always @(posedge clk_100m) begin
|
||||
baseband_i, baseband_q, debug_bb_count);
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
// In ddc_400m.v, add these debug signals:
|
||||
|
||||
`endif
|
||||
|
||||
// In ddc_400m.v, add these debug signals:
|
||||
|
||||
// Debug monitoring (simulation only)
|
||||
`ifdef SIMULATION
|
||||
reg [31:0] debug_adc_count = 0;
|
||||
@@ -723,58 +732,67 @@ always @(posedge clk_100m) begin
|
||||
baseband_i, baseband_q, debug_baseband_count, $time);
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Phase Dithering Module
|
||||
// ============================================================================
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module lfsr_dither_enhanced #(
|
||||
parameter DITHER_WIDTH = 8 // Increased for better dithering
|
||||
)(
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
input wire enable,
|
||||
output wire [DITHER_WIDTH-1:0] dither_out
|
||||
);
|
||||
|
||||
reg [DITHER_WIDTH-1:0] lfsr_reg;
|
||||
reg [15:0] cycle_counter;
|
||||
reg lock_detected;
|
||||
|
||||
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
|
||||
wire feedback;
|
||||
|
||||
generate
|
||||
if (DITHER_WIDTH == 4) begin
|
||||
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
|
||||
end else if (DITHER_WIDTH == 8) begin
|
||||
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
|
||||
end else begin
|
||||
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
|
||||
cycle_counter <= 0;
|
||||
lock_detected <= 0;
|
||||
end else if (enable) begin
|
||||
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
|
||||
cycle_counter <= cycle_counter + 1;
|
||||
|
||||
// Detect LFSR lock after sufficient cycles
|
||||
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
|
||||
lock_detected <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign dither_out = lfsr_reg;
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================================
|
||||
// Enhanced Phase Dithering Module
|
||||
// ============================================================================
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module lfsr_dither_enhanced #(
|
||||
parameter DITHER_WIDTH = 8 // Increased for better dithering
|
||||
)(
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
input wire enable,
|
||||
output wire [DITHER_WIDTH-1:0] dither_out
|
||||
);
|
||||
|
||||
reg [DITHER_WIDTH-1:0] lfsr_reg;
|
||||
reg [15:0] cycle_counter;
|
||||
reg lock_detected;
|
||||
|
||||
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
|
||||
wire feedback;
|
||||
|
||||
generate
|
||||
if (DITHER_WIDTH == 4) begin
|
||||
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
|
||||
end else if (DITHER_WIDTH == 8) begin
|
||||
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
|
||||
end else begin
|
||||
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ============================================================================
|
||||
// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
|
||||
// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
|
||||
// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
|
||||
// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
|
||||
// ============================================================================
|
||||
(* max_fanout = 50 *) reg reset_h = 1'b1;
|
||||
always @(posedge clk) reset_h <= ~reset_n;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset_h) begin
|
||||
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
|
||||
cycle_counter <= 0;
|
||||
lock_detected <= 0;
|
||||
end else if (enable) begin
|
||||
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
|
||||
cycle_counter <= cycle_counter + 1;
|
||||
|
||||
// Detect LFSR lock after sufficient cycles
|
||||
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
|
||||
lock_detected <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign dither_out = lfsr_reg;
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user