Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
Implement iterative single-butterfly FFT engine (fft_engine.v) supporting 1024-pt and 32-pt transforms with quarter-wave twiddle ROM, XPM_MEMORY_TDPRAM for guaranteed BRAM mapping in Vivado, and behavioral model for simulation. Add xfft_32.v AXI-Stream wrapper for doppler_processor integration and dual-branch matched_filter_processing_chain.v (behavioral + synthesis paths). Fix placement failure caused by 68K+ registers from dissolved memory arrays: - doppler_processor.v: extract mem writes to sync-only always block for BRAM - xfft_32.v: extract buffer writes to sync-only always block for LUTRAM Post-implementation: 37K regs (29%), 23K LUTs (37%), 10 BRAM (7%), fully routed. All testbenches pass: fft_engine 12/12, xfft_32 10/10, mf_chain 27/27.
This commit is contained in:
Jason
+240
-33
@@ -1,18 +1,15 @@
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`timescale 1ns / 1ps
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// ============================================================================
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// xfft_32.v — Synthesis stub for Xilinx 32-point FFT IP core
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// xfft_32.v — 32-point FFT with AXI-Stream interface
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// ============================================================================
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// This is a PLACEHOLDER module that provides the port interface expected by
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// doppler_processor.v. It does NOT perform an actual FFT — it simply passes
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// input data through with a one-cycle latency and generates proper AXI-Stream
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// handshake signals.
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//
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// For real hardware, replace this stub with either:
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// (a) A Xilinx FFT IP core generated via Vivado IP Catalog, or
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// (b) A custom synthesizable radix-2 DIT 32-point FFT in Verilog.
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// Wraps the synthesizable fft_engine (radix-2 DIT) with the AXI-Stream port
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// interface expected by doppler_processor.v.
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//
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// Port interface matches the Xilinx LogiCORE IP Fast Fourier Transform
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// (AXI-Stream variant) as instantiated in doppler_processor.v.
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//
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// Data format: {Q[15:0], I[15:0]} packed 32-bit.
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// Config tdata[0]: 1 = forward FFT, 0 = inverse FFT.
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// ============================================================================
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module xfft_32 (
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@@ -36,36 +33,246 @@ module xfft_32 (
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input wire m_axis_data_tready
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);
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// ----------------------------------------------------------------------------
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// Synthesis stub: pass-through with one-cycle latency
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// ----------------------------------------------------------------------------
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// This gives Vivado a real module to synthesize so it can check port
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// connectivity, infer timing paths, and estimate utilization. The actual
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// FFT computation is deferred to IP integration or a custom RTL FFT.
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// ----------------------------------------------------------------------------
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// ============================================================================
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// PARAMETERS
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// ============================================================================
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localparam N = 32;
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localparam LOG2N = 5;
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// Always accept config
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assign s_axis_config_tready = 1'b1;
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// ============================================================================
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// INTERNAL SIGNALS
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// ============================================================================
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// Pipeline registers for data pass-through
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reg [31:0] data_reg;
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reg valid_reg;
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reg last_reg;
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// FSM states
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localparam [2:0] S_IDLE = 3'd0,
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S_CONFIG = 3'd1, // Latch config (fwd/inv)
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S_FEED = 3'd2, // Feed input to FFT engine
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S_WAIT = 3'd3, // Wait for FFT to complete
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S_OUTPUT = 3'd4; // Stream output
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reg [2:0] state;
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// Configuration
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reg inverse_reg;
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// Input buffering
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reg signed [15:0] in_buf_re [0:N-1];
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reg signed [15:0] in_buf_im [0:N-1];
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reg [5:0] in_count; // 0..31 for loading, extra bit for overflow check
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// Output buffering
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reg signed [15:0] out_buf_re [0:N-1];
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reg signed [15:0] out_buf_im [0:N-1];
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reg [5:0] out_count;
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reg [5:0] out_total; // counts how many outputs captured from engine
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// FFT engine interface
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reg fft_start;
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reg fft_inverse;
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reg signed [15:0] fft_din_re, fft_din_im;
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reg fft_din_valid;
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wire signed [15:0] fft_dout_re, fft_dout_im;
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wire fft_dout_valid;
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wire fft_busy;
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wire fft_done;
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// Feed counter for streaming into engine
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reg [5:0] feed_count;
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// ============================================================================
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// FFT ENGINE INSTANCE
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// ============================================================================
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fft_engine #(
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.N(N),
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.LOG2N(LOG2N),
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.DATA_W(16),
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.INTERNAL_W(32),
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.TWIDDLE_W(16),
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.TWIDDLE_FILE("fft_twiddle_32.mem")
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) fft_core (
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.clk(aclk),
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.reset_n(aresetn),
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.start(fft_start),
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.inverse(fft_inverse),
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.din_re(fft_din_re),
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.din_im(fft_din_im),
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.din_valid(fft_din_valid),
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.dout_re(fft_dout_re),
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.dout_im(fft_dout_im),
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.dout_valid(fft_dout_valid),
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.busy(fft_busy),
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.done(fft_done)
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);
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// ============================================================================
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// AXI-STREAM OUTPUTS
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// ============================================================================
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// Config is accepted when idle
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assign s_axis_config_tready = (state == S_IDLE);
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// Output data: {Q, I} packed
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assign m_axis_data_tdata = {out_buf_im[out_count[4:0]], out_buf_re[out_count[4:0]]};
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assign m_axis_data_tvalid = (state == S_OUTPUT) && (out_count < N);
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assign m_axis_data_tlast = (state == S_OUTPUT) && (out_count == N - 1);
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// ============================================================================
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// BUFFER WRITE LOGIC — separate always block, NO async reset
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// Allows Vivado to infer distributed RAM instead of dissolving into registers.
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// ============================================================================
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// Input buffer write enable
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reg in_buf_we;
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reg [4:0] in_buf_waddr;
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reg signed [15:0] in_buf_wdata_re, in_buf_wdata_im;
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// Output buffer write enable
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reg out_buf_we;
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reg [4:0] out_buf_waddr;
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reg signed [15:0] out_buf_wdata_re, out_buf_wdata_im;
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always @(posedge aclk) begin
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if (!aresetn) begin
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data_reg <= 32'd0;
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valid_reg <= 1'b0;
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last_reg <= 1'b0;
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end else begin
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data_reg <= s_axis_data_tdata;
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valid_reg <= s_axis_data_tvalid;
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last_reg <= s_axis_data_tlast;
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if (in_buf_we) begin
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in_buf_re[in_buf_waddr] <= in_buf_wdata_re;
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in_buf_im[in_buf_waddr] <= in_buf_wdata_im;
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end
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if (out_buf_we) begin
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out_buf_re[out_buf_waddr] <= out_buf_wdata_re;
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out_buf_im[out_buf_waddr] <= out_buf_wdata_im;
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end
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end
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assign m_axis_data_tdata = data_reg;
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assign m_axis_data_tvalid = valid_reg;
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assign m_axis_data_tlast = last_reg;
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// ============================================================================
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// MAIN FSM
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// ============================================================================
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always @(posedge aclk or negedge aresetn) begin
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if (!aresetn) begin
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state <= S_IDLE;
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inverse_reg <= 1'b0;
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in_count <= 0;
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out_count <= 0;
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out_total <= 0;
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feed_count <= 0;
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fft_start <= 1'b0;
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fft_inverse <= 1'b0;
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fft_din_re <= 0;
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fft_din_im <= 0;
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fft_din_valid <= 1'b0;
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in_buf_we <= 1'b0;
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in_buf_waddr <= 0;
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in_buf_wdata_re <= 0;
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in_buf_wdata_im <= 0;
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out_buf_we <= 1'b0;
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out_buf_waddr <= 0;
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out_buf_wdata_re <= 0;
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out_buf_wdata_im <= 0;
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end else begin
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// Defaults
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fft_start <= 1'b0;
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fft_din_valid <= 1'b0;
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in_buf_we <= 1'b0;
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out_buf_we <= 1'b0;
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case (state)
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// ================================================================
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S_IDLE: begin
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in_count <= 0;
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if (s_axis_config_tvalid) begin
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// Config tdata[0]: 1=forward, 0=inverse
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// fft_engine: inverse=0 means forward, inverse=1 means inverse
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inverse_reg <= ~s_axis_config_tdata[0];
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state <= S_FEED;
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in_count <= 0;
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feed_count <= 0;
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end
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end
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// ================================================================
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// S_FEED: Buffer all N inputs first, then start engine.
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// ================================================================
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S_FEED: begin
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if (in_count < N) begin
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// Still accepting input data
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if (s_axis_data_tvalid) begin
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in_buf_we <= 1'b1;
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in_buf_waddr <= in_count[4:0];
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in_buf_wdata_re <= s_axis_data_tdata[15:0];
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in_buf_wdata_im <= s_axis_data_tdata[31:16];
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in_count <= in_count + 1;
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end
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end else if (feed_count == 0) begin
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// All N inputs buffered, start the FFT engine
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fft_start <= 1'b1;
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fft_inverse <= inverse_reg;
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feed_count <= 0;
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state <= S_WAIT;
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out_total <= 0;
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end
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end
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// ================================================================
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// S_WAIT: Feed buffered data to engine, then wait for output
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// ================================================================
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S_WAIT: begin
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if (feed_count < N) begin
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fft_din_re <= in_buf_re[feed_count[4:0]];
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fft_din_im <= in_buf_im[feed_count[4:0]];
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fft_din_valid <= 1'b1;
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feed_count <= feed_count + 1;
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end
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// Capture engine outputs
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if (fft_dout_valid && out_total < N) begin
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out_buf_we <= 1'b1;
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out_buf_waddr <= out_total[4:0];
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out_buf_wdata_re <= fft_dout_re;
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out_buf_wdata_im <= fft_dout_im;
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out_total <= out_total + 1;
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end
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// Engine done
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if (fft_done) begin
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state <= S_OUTPUT;
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out_count <= 0;
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end
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end
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// ================================================================
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// S_OUTPUT: Stream buffered results via AXI-Stream master
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// ================================================================
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S_OUTPUT: begin
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if (m_axis_data_tready || !m_axis_data_tvalid) begin
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if (out_count < N) begin
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// m_axis_data_tdata driven combinationally from out_buf
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if (m_axis_data_tready) begin
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out_count <= out_count + 1;
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end
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end
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if (out_count >= N - 1 && m_axis_data_tready) begin
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state <= S_IDLE;
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end
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end
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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// ============================================================================
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// MEMORY INIT (simulation only)
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// ============================================================================
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`ifdef SIMULATION
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integer init_k;
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initial begin
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for (init_k = 0; init_k < N; init_k = init_k + 1) begin
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in_buf_re[init_k] = 0;
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in_buf_im[init_k] = 0;
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out_buf_re[init_k] = 0;
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out_buf_im[init_k] = 0;
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end
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end
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`endif
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endmodule
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