Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

Implement iterative single-butterfly FFT engine (fft_engine.v) supporting
1024-pt and 32-pt transforms with quarter-wave twiddle ROM, XPM_MEMORY_TDPRAM
for guaranteed BRAM mapping in Vivado, and behavioral model for simulation.

Add xfft_32.v AXI-Stream wrapper for doppler_processor integration and
dual-branch matched_filter_processing_chain.v (behavioral + synthesis paths).

Fix placement failure caused by 68K+ registers from dissolved memory arrays:
- doppler_processor.v: extract mem writes to sync-only always block for BRAM
- xfft_32.v: extract buffer writes to sync-only always block for LUTRAM

Post-implementation: 37K regs (29%), 23K LUTs (37%), 10 BRAM (7%), fully routed.
All testbenches pass: fft_engine 12/12, xfft_32 10/10, mf_chain 27/27.

9_Firmware/9_2_FPGA/fft_twiddle_1024.mem

@@ -0,0 +1,259 @@
+// Quarter-wave cosine ROM for 1024-point FFT
+// 256 entries, 16-bit signed Q15 ($readmemh format)
+// cos(2*pi*k/1024) for k = 0..255
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