Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
Implement iterative single-butterfly FFT engine (fft_engine.v) supporting 1024-pt and 32-pt transforms with quarter-wave twiddle ROM, XPM_MEMORY_TDPRAM for guaranteed BRAM mapping in Vivado, and behavioral model for simulation. Add xfft_32.v AXI-Stream wrapper for doppler_processor integration and dual-branch matched_filter_processing_chain.v (behavioral + synthesis paths). Fix placement failure caused by 68K+ registers from dissolved memory arrays: - doppler_processor.v: extract mem writes to sync-only always block for BRAM - xfft_32.v: extract buffer writes to sync-only always block for LUTRAM Post-implementation: 37K regs (29%), 23K LUTs (37%), 10 BRAM (7%), fully routed. All testbenches pass: fft_engine 12/12, xfft_32 10/10, mf_chain 27/27.
This commit is contained in:
Jason
@@ -0,0 +1,606 @@
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`timescale 1ns / 1ps
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/**
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* fft_engine.v
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*
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* Synthesizable parameterized radix-2 DIT FFT/IFFT engine.
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* Iterative single-butterfly architecture with quarter-wave twiddle ROM.
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*
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* Architecture:
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* - LOAD: Accept N input samples, store bit-reversed in BRAM
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* - COMPUTE: LOG2N stages x N/2 butterflies, 2-cycle pipeline:
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* BF_READ: Present BRAM addresses, capture twiddle
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* BF_CALC: BRAM data valid; butterfly compute + writeback
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* - OUTPUT: Stream N results (1/N scaling for IFFT)
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*
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* Data memory uses xpm_memory_tdpram (Xilinx Parameterized Macros) for
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* guaranteed BRAM mapping in synthesis. Under `ifdef SIMULATION, a
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* behavioral Verilog-2001 model replaces the XPM so the design compiles
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* with Icarus Verilog or any non-Xilinx simulator.
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*
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* Clock domain: single clock (clk), active-low async reset (reset_n).
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*/
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module fft_engine #(
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parameter N = 1024,
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parameter LOG2N = 10,
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parameter DATA_W = 16,
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parameter INTERNAL_W = 32,
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parameter TWIDDLE_W = 16,
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parameter TWIDDLE_FILE = "fft_twiddle_1024.mem"
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)(
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input wire clk,
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input wire reset_n,
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// Control
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input wire start,
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input wire inverse,
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// Data input
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input wire signed [DATA_W-1:0] din_re,
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input wire signed [DATA_W-1:0] din_im,
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input wire din_valid,
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// Data output
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output reg signed [DATA_W-1:0] dout_re,
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output reg signed [DATA_W-1:0] dout_im,
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output reg dout_valid,
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// Status
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output wire busy,
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output reg done
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);
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// ============================================================================
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// SAFE WIDTH CONSTANTS
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// ============================================================================
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localparam [LOG2N:0] FFT_N = N;
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localparam [LOG2N:0] FFT_N_HALF = N / 2;
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localparam [LOG2N:0] FFT_N_QTR = N / 4;
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localparam [LOG2N:0] FFT_N_HALF_M1 = N / 2 - 1;
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localparam [LOG2N:0] FFT_N_M1 = N - 1;
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// ============================================================================
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// STATES
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// ============================================================================
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localparam [2:0] ST_IDLE = 3'd0,
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ST_LOAD = 3'd1,
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ST_BF_READ = 3'd2,
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ST_BF_CALC = 3'd3,
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ST_OUTPUT = 3'd4,
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ST_DONE = 3'd5;
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reg [2:0] state;
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assign busy = (state != ST_IDLE);
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// ============================================================================
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// DATA MEMORY DECLARATIONS
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// ============================================================================
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// BRAM read data (registered outputs from port blocks)
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reg signed [INTERNAL_W-1:0] mem_rdata_a_re, mem_rdata_a_im;
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reg signed [INTERNAL_W-1:0] mem_rdata_b_re, mem_rdata_b_im;
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// ============================================================================
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// TWIDDLE ROM
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// ============================================================================
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localparam TW_QUARTER = N / 4;
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localparam TW_ADDR_W = LOG2N - 2;
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(* rom_style = "block" *) reg signed [TWIDDLE_W-1:0] cos_rom [0:TW_QUARTER-1];
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initial begin
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$readmemh(TWIDDLE_FILE, cos_rom);
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end
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// ============================================================================
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// BIT-REVERSE
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// ============================================================================
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function [LOG2N-1:0] bit_reverse;
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input [LOG2N-1:0] val;
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integer b;
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begin
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bit_reverse = 0;
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for (b = 0; b < LOG2N; b = b + 1)
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bit_reverse[LOG2N-1-b] = val[b];
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end
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endfunction
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// ============================================================================
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// COUNTERS AND PIPELINE REGISTERS
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// ============================================================================
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reg [LOG2N-1:0] load_count;
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reg [LOG2N:0] out_count;
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reg [LOG2N-1:0] bfly_count;
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reg [3:0] stage;
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// Registered values (captured in BF_READ, used in BF_CALC)
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reg signed [TWIDDLE_W-1:0] rd_tw_cos, rd_tw_sin;
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reg [LOG2N-1:0] rd_addr_even, rd_addr_odd;
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reg rd_inverse;
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// Half and twiddle stride
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reg [LOG2N-1:0] half_reg;
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reg [LOG2N-1:0] tw_stride_reg;
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// ============================================================================
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// BUTTERFLY ADDRESS COMPUTATION (combinational)
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// ============================================================================
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reg [LOG2N-1:0] bf_addr_even;
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reg [LOG2N-1:0] bf_addr_odd;
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reg [LOG2N-1:0] bf_tw_idx;
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always @(*) begin : bf_addr_calc
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reg [LOG2N-1:0] half_val;
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reg [LOG2N-1:0] idx_val;
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reg [LOG2N-1:0] grp_val;
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half_val = half_reg;
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idx_val = bfly_count & (half_val - 1);
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grp_val = (bfly_count - idx_val);
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bf_addr_even = (grp_val << 1) | idx_val;
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bf_addr_odd = bf_addr_even + half_val;
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bf_tw_idx = idx_val * tw_stride_reg;
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end
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// ============================================================================
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// TWIDDLE LOOKUP (combinational)
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// ============================================================================
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reg signed [TWIDDLE_W-1:0] tw_cos_lookup;
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reg signed [TWIDDLE_W-1:0] tw_sin_lookup;
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always @(*) begin : tw_lookup
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reg [LOG2N-1:0] k;
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reg [LOG2N-1:0] rom_idx;
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k = bf_tw_idx;
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tw_cos_lookup = 0;
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tw_sin_lookup = 0;
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if (k == 0) begin
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tw_cos_lookup = cos_rom[0];
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tw_sin_lookup = {TWIDDLE_W{1'b0}};
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end else if (k == FFT_N_QTR[LOG2N-1:0]) begin
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tw_cos_lookup = {TWIDDLE_W{1'b0}};
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tw_sin_lookup = cos_rom[0];
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end else if (k < FFT_N_QTR[LOG2N-1:0]) begin
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tw_cos_lookup = cos_rom[k[TW_ADDR_W-1:0]];
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rom_idx = FFT_N_QTR[LOG2N-1:0] - k;
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tw_sin_lookup = cos_rom[rom_idx[TW_ADDR_W-1:0]];
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end else begin
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rom_idx = k - FFT_N_QTR[LOG2N-1:0];
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tw_sin_lookup = cos_rom[rom_idx[TW_ADDR_W-1:0]];
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rom_idx = FFT_N_HALF[LOG2N-1:0] - k;
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tw_cos_lookup = -cos_rom[rom_idx[TW_ADDR_W-1:0]];
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end
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end
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// ============================================================================
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// SATURATION
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// ============================================================================
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function signed [DATA_W-1:0] saturate;
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input signed [INTERNAL_W-1:0] val;
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reg signed [INTERNAL_W-1:0] max_pos;
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reg signed [INTERNAL_W-1:0] max_neg;
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begin
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max_pos = (1 << (DATA_W - 1)) - 1;
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max_neg = -(1 << (DATA_W - 1));
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if (val > max_pos)
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saturate = max_pos[DATA_W-1:0];
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else if (val < max_neg)
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saturate = max_neg[DATA_W-1:0];
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else
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saturate = val[DATA_W-1:0];
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end
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endfunction
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// ============================================================================
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// BUTTERFLY COMPUTATION (combinational, for BF_CALC write data)
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// ============================================================================
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reg signed [INTERNAL_W-1:0] bf_t_re, bf_t_im;
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reg signed [INTERNAL_W-1:0] bf_sum_re, bf_sum_im;
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reg signed [INTERNAL_W-1:0] bf_dif_re, bf_dif_im;
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always @(*) begin : bf_compute
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if (!rd_inverse) begin
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bf_t_re = (mem_rdata_b_re * rd_tw_cos + mem_rdata_b_im * rd_tw_sin) >>> (TWIDDLE_W - 1);
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bf_t_im = (mem_rdata_b_im * rd_tw_cos - mem_rdata_b_re * rd_tw_sin) >>> (TWIDDLE_W - 1);
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end else begin
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bf_t_re = (mem_rdata_b_re * rd_tw_cos - mem_rdata_b_im * rd_tw_sin) >>> (TWIDDLE_W - 1);
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bf_t_im = (mem_rdata_b_im * rd_tw_cos + mem_rdata_b_re * rd_tw_sin) >>> (TWIDDLE_W - 1);
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end
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bf_sum_re = mem_rdata_a_re + bf_t_re;
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bf_sum_im = mem_rdata_a_im + bf_t_im;
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bf_dif_re = mem_rdata_a_re - bf_t_re;
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bf_dif_im = mem_rdata_a_im - bf_t_im;
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end
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// ============================================================================
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// BRAM PORT ADDRESS / WE / WDATA — combinational mux (registered signals)
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// ============================================================================
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// Drives port A and port B control signals from FSM state.
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// These are registered (via NBA) so they are stable at the next posedge
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// when the BRAM template blocks sample them. This avoids any NBA race.
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// ============================================================================
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reg bram_we_a;
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reg [LOG2N-1:0] bram_addr_a;
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reg signed [INTERNAL_W-1:0] bram_wdata_a_re;
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reg signed [INTERNAL_W-1:0] bram_wdata_a_im;
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reg bram_we_b;
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reg [LOG2N-1:0] bram_addr_b;
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reg signed [INTERNAL_W-1:0] bram_wdata_b_re;
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reg signed [INTERNAL_W-1:0] bram_wdata_b_im;
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always @(*) begin : bram_port_mux
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// Port A defaults
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bram_we_a = 1'b0;
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bram_addr_a = 0;
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bram_wdata_a_re = 0;
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bram_wdata_a_im = 0;
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// Port B defaults
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bram_we_b = 1'b0;
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bram_addr_b = 0;
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bram_wdata_b_re = 0;
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bram_wdata_b_im = 0;
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case (state)
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ST_LOAD: begin
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bram_we_a = din_valid;
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bram_addr_a = bit_reverse(load_count);
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bram_wdata_a_re = {{(INTERNAL_W-DATA_W){din_re[DATA_W-1]}}, din_re};
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bram_wdata_a_im = {{(INTERNAL_W-DATA_W){din_im[DATA_W-1]}}, din_im};
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end
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ST_BF_READ: begin
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bram_addr_a = bf_addr_even;
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bram_addr_b = bf_addr_odd;
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end
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ST_BF_CALC: begin
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bram_we_a = 1'b1;
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bram_addr_a = rd_addr_even;
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bram_wdata_a_re = bf_sum_re;
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bram_wdata_a_im = bf_sum_im;
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bram_we_b = 1'b1;
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bram_addr_b = rd_addr_odd;
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bram_wdata_b_re = bf_dif_re;
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bram_wdata_b_im = bf_dif_im;
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end
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ST_OUTPUT: begin
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bram_addr_a = out_count[LOG2N-1:0];
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end
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default: begin
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// keep defaults
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end
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endcase
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end
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// ============================================================================
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// DATA MEMORY — True Dual-Port BRAM
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// ============================================================================
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// For synthesis: xpm_memory_tdpram (Xilinx Parameterized Macros)
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// For simulation: behavioral Verilog-2001 model (Icarus-compatible)
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// ============================================================================
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// XPM read-data wires (directly assigned to rdata regs below)
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wire [INTERNAL_W-1:0] xpm_douta_re, xpm_doutb_re;
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wire [INTERNAL_W-1:0] xpm_douta_im, xpm_doutb_im;
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always @(*) begin
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mem_rdata_a_re = $signed(xpm_douta_re);
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mem_rdata_a_im = $signed(xpm_douta_im);
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mem_rdata_b_re = $signed(xpm_doutb_re);
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mem_rdata_b_im = $signed(xpm_doutb_im);
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end
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`ifndef FFT_XPM_BRAM
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// ----------------------------------------------------------------------------
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// Default: behavioral TDP model (works with Icarus Verilog -g2001)
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// For Vivado synthesis, define FFT_XPM_BRAM to use xpm_memory_tdpram.
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// ----------------------------------------------------------------------------
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reg [INTERNAL_W-1:0] sim_mem_re [0:N-1];
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reg [INTERNAL_W-1:0] sim_mem_im [0:N-1];
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// Port A
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reg [INTERNAL_W-1:0] sim_douta_re, sim_douta_im;
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always @(posedge clk) begin
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if (bram_we_a) begin
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sim_mem_re[bram_addr_a] <= bram_wdata_a_re;
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sim_mem_im[bram_addr_a] <= bram_wdata_a_im;
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end
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sim_douta_re <= sim_mem_re[bram_addr_a];
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sim_douta_im <= sim_mem_im[bram_addr_a];
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end
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assign xpm_douta_re = sim_douta_re;
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assign xpm_douta_im = sim_douta_im;
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// Port B
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reg [INTERNAL_W-1:0] sim_doutb_re, sim_doutb_im;
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always @(posedge clk) begin
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if (bram_we_b) begin
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sim_mem_re[bram_addr_b] <= bram_wdata_b_re;
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sim_mem_im[bram_addr_b] <= bram_wdata_b_im;
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end
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sim_doutb_re <= sim_mem_re[bram_addr_b];
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sim_doutb_im <= sim_mem_im[bram_addr_b];
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end
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assign xpm_doutb_re = sim_doutb_re;
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assign xpm_doutb_im = sim_doutb_im;
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integer init_i;
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initial begin
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for (init_i = 0; init_i < N; init_i = init_i + 1) begin
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sim_mem_re[init_i] = 0;
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sim_mem_im[init_i] = 0;
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end
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end
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`else
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// ----------------------------------------------------------------------------
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// Synthesis: xpm_memory_tdpram — guaranteed BRAM mapping
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// Enabled when FFT_XPM_BRAM is defined (e.g. in Vivado TCL script).
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// ----------------------------------------------------------------------------
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// Note: Vivado auto-finds XPM library; no `include needed.
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// Two instances: one for real, one for imaginary.
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// WRITE_MODE = "write_first" matches the behavioral TDP template.
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// READ_LATENCY = 1 (registered output).
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// ----------------------------------------------------------------------------
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xpm_memory_tdpram #(
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.ADDR_WIDTH_A (LOG2N),
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.ADDR_WIDTH_B (LOG2N),
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.AUTO_SLEEP_TIME (0),
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.BYTE_WRITE_WIDTH_A (INTERNAL_W),
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.BYTE_WRITE_WIDTH_B (INTERNAL_W),
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.CASCADE_HEIGHT (0),
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.CLOCKING_MODE ("common_clock"),
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.ECC_BIT_RANGE ("7:0"),
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.ECC_MODE ("no_ecc"),
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.ECC_TYPE ("none"),
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.IGNORE_INIT_SYNTH (0),
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.MEMORY_INIT_FILE ("none"),
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.MEMORY_INIT_PARAM ("0"),
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.MEMORY_OPTIMIZATION ("true"),
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.MEMORY_PRIMITIVE ("block"),
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.MEMORY_SIZE (N * INTERNAL_W),
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.MESSAGE_CONTROL (0),
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.RAM_DECOMP ("auto"),
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.READ_DATA_WIDTH_A (INTERNAL_W),
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.READ_DATA_WIDTH_B (INTERNAL_W),
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.READ_LATENCY_A (1),
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.READ_LATENCY_B (1),
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.READ_RESET_VALUE_A ("0"),
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.READ_RESET_VALUE_B ("0"),
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.RST_MODE_A ("SYNC"),
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.RST_MODE_B ("SYNC"),
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.SIM_ASSERT_CHK (0),
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.USE_EMBEDDED_CONSTRAINT (0),
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.USE_MEM_INIT (1),
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.USE_MEM_INIT_MMI (0),
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.WAKEUP_TIME ("disable_sleep"),
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.WRITE_DATA_WIDTH_A (INTERNAL_W),
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.WRITE_DATA_WIDTH_B (INTERNAL_W),
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.WRITE_MODE_A ("read_first"),
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.WRITE_MODE_B ("read_first"),
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.WRITE_PROTECT (1)
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) u_bram_re (
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.clka (clk),
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.clkb (clk),
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.rsta (1'b0),
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.rstb (1'b0),
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.ena (1'b1),
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.enb (1'b1),
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.regcea (1'b1),
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.regceb (1'b1),
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.addra (bram_addr_a),
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.addrb (bram_addr_b),
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.dina (bram_wdata_a_re),
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.dinb (bram_wdata_b_re),
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.wea (bram_we_a),
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.web (bram_we_b),
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.douta (xpm_douta_re),
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.doutb (xpm_doutb_re),
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||||
.injectdbiterra (1'b0),
|
||||
.injectdbiterrb (1'b0),
|
||||
.injectsbiterra (1'b0),
|
||||
.injectsbiterrb (1'b0),
|
||||
.sbiterra (),
|
||||
.sbiterrb (),
|
||||
.dbiterra (),
|
||||
.dbiterrb (),
|
||||
.sleep (1'b0)
|
||||
);
|
||||
|
||||
xpm_memory_tdpram #(
|
||||
.ADDR_WIDTH_A (LOG2N),
|
||||
.ADDR_WIDTH_B (LOG2N),
|
||||
.AUTO_SLEEP_TIME (0),
|
||||
.BYTE_WRITE_WIDTH_A (INTERNAL_W),
|
||||
.BYTE_WRITE_WIDTH_B (INTERNAL_W),
|
||||
.CASCADE_HEIGHT (0),
|
||||
.CLOCKING_MODE ("common_clock"),
|
||||
.ECC_BIT_RANGE ("7:0"),
|
||||
.ECC_MODE ("no_ecc"),
|
||||
.ECC_TYPE ("none"),
|
||||
.IGNORE_INIT_SYNTH (0),
|
||||
.MEMORY_INIT_FILE ("none"),
|
||||
.MEMORY_INIT_PARAM ("0"),
|
||||
.MEMORY_OPTIMIZATION ("true"),
|
||||
.MEMORY_PRIMITIVE ("block"),
|
||||
.MEMORY_SIZE (N * INTERNAL_W),
|
||||
.MESSAGE_CONTROL (0),
|
||||
.RAM_DECOMP ("auto"),
|
||||
.READ_DATA_WIDTH_A (INTERNAL_W),
|
||||
.READ_DATA_WIDTH_B (INTERNAL_W),
|
||||
.READ_LATENCY_A (1),
|
||||
.READ_LATENCY_B (1),
|
||||
.READ_RESET_VALUE_A ("0"),
|
||||
.READ_RESET_VALUE_B ("0"),
|
||||
.RST_MODE_A ("SYNC"),
|
||||
.RST_MODE_B ("SYNC"),
|
||||
.SIM_ASSERT_CHK (0),
|
||||
.USE_EMBEDDED_CONSTRAINT (0),
|
||||
.USE_MEM_INIT (1),
|
||||
.USE_MEM_INIT_MMI (0),
|
||||
.WAKEUP_TIME ("disable_sleep"),
|
||||
.WRITE_DATA_WIDTH_A (INTERNAL_W),
|
||||
.WRITE_DATA_WIDTH_B (INTERNAL_W),
|
||||
.WRITE_MODE_A ("read_first"),
|
||||
.WRITE_MODE_B ("read_first"),
|
||||
.WRITE_PROTECT (1)
|
||||
) u_bram_im (
|
||||
.clka (clk),
|
||||
.clkb (clk),
|
||||
.rsta (1'b0),
|
||||
.rstb (1'b0),
|
||||
.ena (1'b1),
|
||||
.enb (1'b1),
|
||||
.regcea (1'b1),
|
||||
.regceb (1'b1),
|
||||
.addra (bram_addr_a),
|
||||
.addrb (bram_addr_b),
|
||||
.dina (bram_wdata_a_im),
|
||||
.dinb (bram_wdata_b_im),
|
||||
.wea (bram_we_a),
|
||||
.web (bram_we_b),
|
||||
.douta (xpm_douta_im),
|
||||
.doutb (xpm_doutb_im),
|
||||
.injectdbiterra (1'b0),
|
||||
.injectdbiterrb (1'b0),
|
||||
.injectsbiterra (1'b0),
|
||||
.injectsbiterrb (1'b0),
|
||||
.sbiterra (),
|
||||
.sbiterrb (),
|
||||
.dbiterra (),
|
||||
.dbiterrb (),
|
||||
.sleep (1'b0)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
// ============================================================================
|
||||
// OUTPUT PIPELINE
|
||||
// ============================================================================
|
||||
reg out_pipe_valid;
|
||||
reg out_pipe_inverse;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_pipe_valid <= 1'b0;
|
||||
out_pipe_inverse <= 1'b0;
|
||||
end else begin
|
||||
out_pipe_valid <= (state == ST_OUTPUT) && (out_count <= FFT_N_M1[LOG2N-1:0]);
|
||||
out_pipe_inverse <= inverse;
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// MAIN FSM
|
||||
// ============================================================================
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
state <= ST_IDLE;
|
||||
load_count <= 0;
|
||||
out_count <= 0;
|
||||
bfly_count <= 0;
|
||||
stage <= 0;
|
||||
half_reg <= 1;
|
||||
tw_stride_reg <= FFT_N_HALF[LOG2N-1:0];
|
||||
dout_re <= 0;
|
||||
dout_im <= 0;
|
||||
dout_valid <= 0;
|
||||
done <= 0;
|
||||
rd_tw_cos <= 0;
|
||||
rd_tw_sin <= 0;
|
||||
rd_addr_even <= 0;
|
||||
rd_addr_odd <= 0;
|
||||
rd_inverse <= 0;
|
||||
end else begin
|
||||
dout_valid <= 1'b0;
|
||||
done <= 1'b0;
|
||||
|
||||
case (state)
|
||||
|
||||
ST_IDLE: begin
|
||||
if (start) begin
|
||||
state <= ST_LOAD;
|
||||
load_count <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
ST_LOAD: begin
|
||||
if (din_valid) begin
|
||||
if (load_count == FFT_N_M1[LOG2N-1:0]) begin
|
||||
state <= ST_BF_READ;
|
||||
stage <= 0;
|
||||
bfly_count <= 0;
|
||||
half_reg <= 1;
|
||||
tw_stride_reg <= FFT_N_HALF[LOG2N-1:0];
|
||||
end else begin
|
||||
load_count <= load_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ST_BF_READ: begin
|
||||
rd_tw_cos <= tw_cos_lookup;
|
||||
rd_tw_sin <= tw_sin_lookup;
|
||||
rd_addr_even <= bf_addr_even;
|
||||
rd_addr_odd <= bf_addr_odd;
|
||||
rd_inverse <= inverse;
|
||||
state <= ST_BF_CALC;
|
||||
end
|
||||
|
||||
ST_BF_CALC: begin
|
||||
if (bfly_count == FFT_N_HALF_M1[LOG2N-1:0]) begin
|
||||
bfly_count <= 0;
|
||||
if (stage == LOG2N - 1) begin
|
||||
state <= ST_OUTPUT;
|
||||
out_count <= 0;
|
||||
end else begin
|
||||
stage <= stage + 1;
|
||||
half_reg <= half_reg << 1;
|
||||
tw_stride_reg <= tw_stride_reg >> 1;
|
||||
state <= ST_BF_READ;
|
||||
end
|
||||
end else begin
|
||||
bfly_count <= bfly_count + 1;
|
||||
state <= ST_BF_READ;
|
||||
end
|
||||
end
|
||||
|
||||
ST_OUTPUT: begin
|
||||
if (out_count <= FFT_N_M1[LOG2N-1:0]) begin
|
||||
out_count <= out_count + 1;
|
||||
end
|
||||
|
||||
if (out_pipe_valid) begin
|
||||
if (out_pipe_inverse) begin
|
||||
dout_re <= saturate(mem_rdata_a_re >>> LOG2N);
|
||||
dout_im <= saturate(mem_rdata_a_im >>> LOG2N);
|
||||
end else begin
|
||||
dout_re <= saturate(mem_rdata_a_re);
|
||||
dout_im <= saturate(mem_rdata_a_im);
|
||||
end
|
||||
dout_valid <= 1'b1;
|
||||
end
|
||||
|
||||
if (out_count > FFT_N_M1[LOG2N-1:0] && !out_pipe_valid) begin
|
||||
state <= ST_DONE;
|
||||
end
|
||||
end
|
||||
|
||||
ST_DONE: begin
|
||||
done <= 1'b1;
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
|
||||
default: state <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user