fix(pre-bringup): second-batch P1/P2/P3 audit findings

Addresses the remaining actionable items from
docs/DEVELOP_AUDIT_2026-04-19.md after commit 3f47d1e.

XDC (dead waivers — F-0.4, F-0.5, F-0.6, F-0.7):
- ft_clkout_IBUF CLOCK_DEDICATED_ROUTE now uses hierarchical filter;
  flat net name did not exist post-synth.
- reset_sync_reg[*] false-path rewritten to walk hierarchy and filter
  on CLR/PRE pins.
- adc_clk_mmcm.xdc ft601_clk_in references replaced with foreach-loop
  over real USB clock names, gated on -quiet existence.
- MMCM LOCKED waiver uses REF_PIN_NAME filter instead of the
  previously-missing u_core/ literal path.

CDC (F-1.1, F-1.2, F-1.3):
- Documented the quasi-static-bus stability invariant above the
  FT601 cmd_valid toggle block.
- cdc_adc_to_processing gains an `overrun` output; the two CIC->FIR
  instances feed a sticky cdc_cic_fir_overrun flag surfaced on
  gpio_dig5 so silent sample drops become visible to the MCU.
- Removed the dead mixers_enable synchronizer in ddc_400m.v; the _sync
  output was unused and every caller ties the port to 1'b1.

Diagnostics (F-6.4):
- range_bin_decimator watchdog_timeout plumbed through receiver
  and top-level, OR'd into gpio_dig5.

ADAR (F-4.7):
- delayUs() replaced with DWT cycle counter; self-initialising
  TRCENA/CYCCNTENA, overflow-safe unsigned subtraction.

Regression: tb_cdc_modules.v 57/57 passes under iverilog after
the cdc_modules.v change. Remote Vivado verification in progress.

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp

@@ -735,10 +735,21 @@ void ADAR1000Manager::setLNABias(bool enable) {
 }
 
 void ADAR1000Manager::delayUs(uint32_t microseconds) {
-    // Simple implementation - for F7 @ 216MHz, each loop ~7 cycles ≈ 0.032us
-    volatile uint32_t cycles = microseconds * 10; // Adjust this multiplier for your clock
-    while (cycles--) {
-        __NOP();
+    // Audit F-4.7: the prior implementation was a calibrated __NOP() busy-loop
+    // that silently drifted with compiler optimization, cache state, and flash
+    // wait-states. The ADAR1000 PLL/TX settling times require a real clock, so
+    // we poll the DWT cycle counter instead. One-time TRCENA/CYCCNTENA enable
+    // is idempotent; subsequent calls skip the init branch via DWT->CTRL read.
+    if ((DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) == 0U) {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        DWT->CYCCNT       = 0U;
+        DWT->CTRL        |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+    const uint32_t cycles_per_us = SystemCoreClock / 1000000U;
+    const uint32_t start         = DWT->CYCCNT;
+    const uint32_t target        = microseconds * cycles_per_us;
+    while ((DWT->CYCCNT - start) < target) {
+        /* CYCCNT wraps cleanly modulo 2^32 — subtraction stays correct. */
     }
 }