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Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

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CDC fixes across 6 RTL files based on post-implementation report_cdc analysis:
- P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC
       in radar_transmitter, add ft601 reset synchronizer and USB holding
       registers with proper edge detection in usb_data_interface
- P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC,
       fix USB valid edge detect to use fully-synced signal
- P2: register Gray encoding in cdc_adc_to_processing source domain, sync
       ft601_txe and stm32_mixers_enable for status_reg in radar_system_top
- Safety: add in_bin_count overflow guard in range_bin_decimator to prevent
          downstream BRAM corruption

All 13 regression test suites pass (159 individual tests).
This commit is contained in:
Jason
2026-03-17 13:48:47 +02:00
parent fb59e98737
commit 5fd632bc47
9 changed files with 2299 additions and 2098 deletions
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9_Firmware/9_2_FPGA/scripts/run_cdc_and_netlist.tcl
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# run_cdc_and_netlist.tcl
# Opens the routed design and runs:
# 1. report_cdc — detailed CDC analysis to investigate TIMING-9
# 2. write_verilog — post-synthesis functional simulation netlist
#
# Usage: vivado -mode batch -source run_cdc_and_netlist.tcl
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project"
set report_dir "${project_dir}/reports_impl"
# Open the routed checkpoint
open_checkpoint ${project_dir}/aeris10_radar.runs/impl_1/radar_system_top_routed.dcp
# ============================================================================
# 1. report_cdc — identify all CDC crossings and the TIMING-9 source
# ============================================================================
puts "INFO: Running report_cdc..."
report_cdc -details -file ${report_dir}/cdc_report.txt
# ============================================================================
# 2. Write post-synthesis functional simulation netlist
# ============================================================================
puts "INFO: Writing post-synthesis functional sim netlist..."
# Post-synthesis (from synth checkpoint) — simpler, no routing delays
open_checkpoint ${project_dir}/aeris10_radar.runs/synth_1/radar_system_top.dcp
write_verilog -force -mode funcsim \
${project_dir}/sim/post_synth_funcsim.v
# Also write SDF for timing sim (from routed checkpoint)
open_checkpoint ${project_dir}/aeris10_radar.runs/impl_1/radar_system_top_routed.dcp
write_verilog -force -mode timesim \
${project_dir}/sim/post_impl_timesim.v
write_sdf -force \
${project_dir}/sim/post_impl_timesim.sdf
puts "INFO: All reports and netlists generated."
puts "INFO: CDC report: ${report_dir}/cdc_report.txt"
puts "INFO: Post-synth sim: ${project_dir}/sim/post_synth_funcsim.v"
puts "INFO: Post-impl sim: ${project_dir}/sim/post_impl_timesim.v"
puts "INFO: SDF: ${project_dir}/sim/post_impl_timesim.sdf"