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Add 8 Verilog testbenches with full coverage (144/144 pass)

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Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).

Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
This commit is contained in:
Jason
2026-03-15 06:14:11 +02:00
parent 76183e2e95
commit 558f49cd4a
21 changed files with 8787 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/tb/nco_quadrature.csv
+41
View File
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sample,sin,cos,mag_sq
0,14732,28898,1052126228
1,18868,26319,1048691185
2,22594,23170,1047337736
3,26319,18868,1048691185
4,28898,14732,1052126228
5,31113,9512,1058496913
6,32285,4808,1065438089
7,32757,0,1073021049
8,4808,-32285,1065438089
9,9512,-31113,1058496913
10,14732,-28898,1052126228
11,18868,-26319,1048691185
12,22594,-23170,1047337736
13,26319,-18868,1048691185
14,28898,-14732,1052126228
15,31113,-9512,1058496913
16,32285,-4808,1065438089
17,32757,0,1073021049
18,-32285,-4808,1065438089
19,-31113,-9512,1058496913
20,-28898,-14732,1052126228
21,-26319,-18868,1048691185
22,-23170,-22594,1047337736
23,-18868,-26319,1048691185
24,-14732,-28898,1052126228
25,-9512,-31113,1058496913
26,-4808,-32285,1065438089
27,0,-32757,1073021049
28,-32285,4808,1065438089
29,-31113,9512,1058496913
30,-28898,14732,1052126228
31,-26319,18868,1048691185
32,-23170,22594,1047337736
33,-18868,26319,1048691185
34,-14732,28898,1052126228
35,-9512,31113,1058496913
36,-4808,32285,1065438089
37,0,32757,1073021049
38,4808,32285,1065438089
39,9512,31113,1058496913
1 sample sin cos mag_sq
2 0 14732 28898 1052126228
3 1 18868 26319 1048691185
4 2 22594 23170 1047337736
5 3 26319 18868 1048691185
6 4 28898 14732 1052126228
7 5 31113 9512 1058496913
8 6 32285 4808 1065438089
9 7 32757 0 1073021049
10 8 4808 -32285 1065438089
11 9 9512 -31113 1058496913
12 10 14732 -28898 1052126228
13 11 18868 -26319 1048691185
14 12 22594 -23170 1047337736
15 13 26319 -18868 1048691185
16 14 28898 -14732 1052126228
17 15 31113 -9512 1058496913
18 16 32285 -4808 1065438089
19 17 32757 0 1073021049
20 18 -32285 -4808 1065438089
21 19 -31113 -9512 1058496913
22 20 -28898 -14732 1052126228
23 21 -26319 -18868 1048691185
24 22 -23170 -22594 1047337736
25 23 -18868 -26319 1048691185
26 24 -14732 -28898 1052126228
27 25 -9512 -31113 1058496913
28 26 -4808 -32285 1065438089
29 27 0 -32757 1073021049
30 28 -32285 4808 1065438089
31 29 -31113 9512 1058496913
32 30 -28898 14732 1052126228
33 31 -26319 18868 1048691185
34 32 -23170 22594 1047337736
35 33 -18868 26319 1048691185
36 34 -14732 28898 1052126228
37 35 -9512 31113 1058496913
38 36 -4808 32285 1065438089
39 37 0 32757 1073021049
40 38 4808 32285 1065438089
41 39 9512 31113 1058496913