add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit
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Jason
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# AERIS-10 FT601 Integration Dev Bitstream
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**File:** `te0713-te0701-umft601x-dev-2026-03-21.bit`
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**Tag:** `v0.1.8-te0713-ft601-dev`
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**Date:** 2026-03-21
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**Target:** XC7A200T-2FBG484C (TE0713-03) on TE0701-06 carrier + UMFT601X-B FMC LPC
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## Build Summary
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| Metric | Value |
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|--------|-------|
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| WNS (setup) | +0.059 ns |
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| WHS (hold) | +0.121 ns |
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| WPWS (pulse width) | +4.500 ns |
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| Failing endpoints | 0 |
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| DRC errors | 0 |
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| Clock | ft601_clk_in 100 MHz (10 ns period) |
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| Strategy | Performance_ExplorePostRoutePhysOpt |
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| Vivado | 2025.2 |
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## What This Bitstream Does
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- Instantiates `usb_data_interface.v` (full FT601 USB data path) via a thin
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wrapper (`radar_system_top_te0713_umft601x_dev.v`)
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- Generates synthetic test data: range profile packets (counter XOR pattern),
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optional Doppler and CFAR packets, controlled by host commands
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- Responds to USB host commands (stream control 0x04, status request 0xFF)
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- Drives `ft601_gpio0` with a ~6 Hz heartbeat (counter bit 24)
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- Drives `ft601_chip_reset_n` after power-on reset (32k clock cycles)
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- `ft601_wakeup_n` held high (inactive)
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## Hardware Setup
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1. TE0713-03 mounted on TE0701-06 carrier
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2. UMFT601X-B plugged into TE0701 J10 (FMC LPC connector)
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3. TE0701 VIOTB = 3.3V (jumper configuration)
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4. UMFT601X-B jumpers: JP1=open, JP2=2-3, JP3=open, JP6=short (3.3V),
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JP4=2-3, JP5=2-3 (245 Sync FIFO mode)
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5. USB 3.0 Micro-B cable from UMFT601X-B to host PC
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6. Trenz programming USB for JTAG
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## Programming
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```
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# Open Vivado Hardware Manager
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open_hw_manager
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connect_hw_server
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open_hw_target
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set_property PROGRAM.FILE {te0713-te0701-umft601x-dev-2026-03-21.bit} [current_hw_device]
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program_hw_devices [current_hw_device]
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```
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## Verification Steps
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1. After programming, check `ft601_gpio0` toggles (~6 Hz) — confirms FPGA running
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2. On host PC, FT601 should enumerate as USB 3.0 device (VID 0x0403, PID 0x601F)
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3. Use FTDI D3XX driver / `ftd3xx` Python library to read data:
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- Open device, set pipe to channel 0
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- Read should return 32-bit words with test pattern packets
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- Packet header: `0xAE10xxxx` where xxxx = packet type
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## Timing Closure Notes
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Previous builds failed setup timing due to source-synchronous clock skew:
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- The FT601 clock enters via IBUF+BUFG (~5 ns insertion delay)
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- `set_output_delay` referenced to `ft601_clk_in` created a false ~5 ns
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skew penalty (source has insertion, destination at port has 0)
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- Fixed by using `set_max_delay -datapath_only` for output constraints,
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which constrains the register-to-pad path directly (7.5 ns budget)
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- Input delays still use `set_input_delay` referenced to `ft601_clk_in`
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(correct direction: FT601 drives data, FPGA samples after IBUF+BUFG)
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## Source Files
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- `9_Firmware/9_2_FPGA/radar_system_top_te0713_umft601x_dev.v` — wrapper top
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- `9_Firmware/9_2_FPGA/usb_data_interface.v` — FT601 USB data interface
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- `9_Firmware/9_2_FPGA/constraints/te0713_te0701_umft601x.xdc` — FMC LPC constraints
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- `9_Firmware/9_2_FPGA/scripts/build_te0713_umft601x_dev.tcl` — build script
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Load Diff
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@@ -44,7 +44,7 @@
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</tr>
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</thead>
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<tbody>
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<tr><td>1</td><td>Freeze known-good firmware and bitstream baselines</td><td>Tracked commit, named artifact set, and repeatable programming flow are available</td><td>Git commit, bitstream path, reports, programming TCL; current heartbeat image at <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code></td></tr>
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<tr><td>1</td><td>Freeze known-good firmware and bitstream baselines</td><td>Tracked commit, named artifact set, and repeatable programming flow are available</td><td>Git commit, bitstream path, reports, programming TCL; heartbeat image at <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code>; FT601 integration dev image at <code>docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit</code> (WNS +0.059 ns, timing clean)</td></tr>
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<tr><td>2</td><td>Preserve clean implementation constraints</td><td>Positive WNS/WHS/WPWS, XDCB-5 cleared, only documented methodology residue remains</td><td>Timing summary and methodology report</td></tr>
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<tr><td>3</td><td>Keep regressions green before board arrival</td><td>MCU host tests and FPGA regression/integration suites pass on the tracked tree</td><td>15/15 MCU and 18/18 FPGA logs</td></tr>
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<tr><td>4</td><td>Make first-power-on behavior observable</td><td>Clock, LO, beamformer, PA, and USB status can be identified from logs or status outputs</td><td>DIAG coverage, status fields, ILA/debug plan</td></tr>
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@@ -39,6 +39,11 @@
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</tr>
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</thead>
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<tbody>
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<tr>
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<td><code>TBD</code> <strong>v0.1.8-te0713-ft601-dev</strong></td>
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<td>TE0713/TE0701 + UMFT601X-B FT601 integration dev bitstream</td>
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<td>First timing-clean FT601 USB integration build for the Trenz + UMFT601X-B FMC LPC stack. Wrapper module (<code>radar_system_top_te0713_umft601x_dev</code>) instantiates the full <code>usb_data_interface</code> with synthetic test data (range/Doppler/CFAR packets). Timing closure achieved after fixing source-synchronous clock skew: replaced <code>set_output_delay</code> with <code>set_max_delay -datapath_only</code> for outputs, removed erroneous <code>set_input_delay</code> on output-only <code>ft601_be[*]</code>. WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors. Strategy: <code>Performance_ExplorePostRoutePhysOpt</code>. Vivado 2025.2. Bitstream: <code>docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit</code>.</td>
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</tr>
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<tr>
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<td><code>TBD</code> <strong>v0.1.7-te0713-heartbeat</strong></td>
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<td>TE0713/TE0701 minimal heartbeat bring-up bitstream</td>
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