add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit
This commit is contained in:
Jason
@@ -217,7 +217,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports {ft601_gpio1}]
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# --------------------------------------------------------------------------
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# FT601 input delays (relative to ft601_clk_in, 100 MHz)
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# FT601 datasheet: Tco max = 7.0 ns, Tco min = 1.0 ns
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# FT601 datasheet (245 Sync FIFO mode): Tco max = 7.0 ns, Tco min = 1.0 ns
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# NOTE: ft601_data is bidirectional — input delay applies during READ ops.
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# ft601_be is output-only in this write-only design; no set_input_delay.
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# --------------------------------------------------------------------------
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set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_data[*]}]
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_data[*]}]
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@@ -225,34 +227,79 @@ set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_tx
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_txe}]
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set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_rxf}]
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_rxf}]
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set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_be[*]}]
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_be[*]}]
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# ft601_be[*] is output-only — removed erroneous set_input_delay (was causing
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# critical warnings and dropped constraints in previous build)
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# --------------------------------------------------------------------------
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# FT601 output delays
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# For WRITE: FPGA drives data on ft601_clk_in edges (same clock domain).
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# FT601 Tsu = 3.0 ns, Th = 0.5 ns
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# Using ft601_clk_in directly (no ODDR forwarded clock on FMC path).
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# FT601 output timing — source-synchronous, datapath-only constraints
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# --------------------------------------------------------------------------
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# The FT601 provides its own 100 MHz clock (D_CLK) and samples data on
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# the next rising edge of that same clock. The FPGA receives D_CLK through
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# IBUF→BUFG (~5 ns insertion), but this insertion delay is COMMON to both
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# the data launch (register clocked by BUFG output) and the data capture
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# (FT601 sampling on the same physical clock edge).
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#
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# Using set_output_delay with the real clock creates a false ~5 ns skew
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# penalty. Using a virtual clock doesn't help because Vivado still sees
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# the IBUF+BUFG insertion on the source side.
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#
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# Instead, we use set_max_delay -datapath_only to constrain the
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# register-to-pad delay directly. The budget is:
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# Tperiod(10 ns) - Tsu(2.0 ns) - Tboard_margin(0.5 ns) = 7.5 ns
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# This ensures data arrives at the FT601 pad with 2.5 ns margin before
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# the next clock edge.
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#
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# For hold (min delay): We use set_min_delay. The FT601 Th = 0.5 ns.
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# The data must not change until 0.5 ns after the CURRENT clock edge.
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# Since the register launches on the clock edge and the pad delay is
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# always positive (>= 1 ns), hold is inherently met. We set min = 0
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# to be safe.
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# --------------------------------------------------------------------------
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# Remove any output_delay on these ports (clean slate — the constraints
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# below supersede them)
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# Data bus
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_data[*]}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_data[*]}] 0.000
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# Byte enable
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_be[*]}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_be[*]}] 0.000
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# Write strobe
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_wr_n}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_wr_n}] 0.000
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# Read strobe
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_rd_n}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_rd_n}] 0.000
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# Output enable
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_oe_n}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_oe_n}] 0.000
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# --------------------------------------------------------------------------
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# Note: Input delays still reference ft601_clk_in (correct for inputs,
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# where the FT601 drives data relative to its clock and the FPGA samples
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# after IBUF+BUFG insertion — the pessimistic direction Vivado handles
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# correctly).
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# --------------------------------------------------------------------------
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set_output_delay -clock [get_clocks ft601_clk_in] -max 3.500 [get_ports {ft601_data[*]}]
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set_output_delay -clock [get_clocks ft601_clk_in] -min 0.000 [get_ports {ft601_data[*]}]
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set_output_delay -clock [get_clocks ft601_clk_in] -max 3.500 [get_ports {ft601_be[*]}]
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set_output_delay -clock [get_clocks ft601_clk_in] -min 0.000 [get_ports {ft601_be[*]}]
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set_output_delay -clock [get_clocks ft601_clk_in] -max 3.500 [get_ports {ft601_wr_n}]
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set_output_delay -clock [get_clocks ft601_clk_in] -min 0.000 [get_ports {ft601_wr_n}]
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set_output_delay -clock [get_clocks ft601_clk_in] -max 3.500 [get_ports {ft601_rd_n}]
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set_output_delay -clock [get_clocks ft601_clk_in] -min 0.000 [get_ports {ft601_rd_n}]
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set_output_delay -clock [get_clocks ft601_clk_in] -max 3.500 [get_ports {ft601_oe_n}]
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set_output_delay -clock [get_clocks ft601_clk_in] -min 0.000 [get_ports {ft601_oe_n}]
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# --------------------------------------------------------------------------
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# IOB packing for timing — same strategy as production XDC
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# Use -quiet because register names depend on synthesis elaboration;
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# a -quiet miss is non-fatal, but the constraint logs should be checked.
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# --------------------------------------------------------------------------
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_data_out_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_be_reg*}]
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set_property IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_wr_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_wr_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_rd_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_oe_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_siwu_n_reg*}]
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# --------------------------------------------------------------------------
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# Async / false paths — chip reset and wakeup are not timing-critical
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# --------------------------------------------------------------------------
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set_false_path -to [get_ports {ft601_chip_reset_n}]
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set_false_path -to [get_ports {ft601_wakeup_n}]
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set_false_path -to [get_ports {ft601_gpio0}]
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set_false_path -to [get_ports {ft601_gpio1}]
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# --------------------------------------------------------------------------
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# NOTES ON RTL ADAPTATION FOR FMC BUILD
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@@ -0,0 +1,144 @@
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`timescale 1ns / 1ps
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module radar_system_top_te0713_umft601x_dev (
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input wire ft601_clk_in,
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inout wire [31:0] ft601_data,
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output wire [3:0] ft601_be,
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input wire ft601_txe,
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input wire ft601_rxf,
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output wire ft601_wr_n,
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output wire ft601_rd_n,
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output wire ft601_oe_n,
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output wire ft601_siwu_n,
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output wire ft601_chip_reset_n,
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output wire ft601_wakeup_n,
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output wire ft601_gpio0,
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output wire ft601_gpio1
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);
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reg [15:0] por_counter = 16'd0;
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reg [31:0] hb_counter = 32'd0;
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reg [15:0] packet_div = 16'd0;
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reg [2:0] stream_control_reg = 3'b001;
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reg status_request_reg = 1'b0;
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reg [31:0] range_profile_reg = 32'd0;
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reg range_valid_reg = 1'b0;
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reg [15:0] doppler_real_reg = 16'd0;
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reg [15:0] doppler_imag_reg = 16'd0;
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reg doppler_valid_reg = 1'b0;
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reg cfar_detection_reg = 1'b0;
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reg cfar_valid_reg = 1'b0;
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wire sys_reset_n;
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wire [31:0] cmd_data;
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wire cmd_valid;
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wire [7:0] cmd_opcode;
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wire [7:0] cmd_addr;
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wire [15:0] cmd_value;
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wire ft601_clk_out_unused;
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wire ft601_txe_n_unused;
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wire ft601_rxf_n_unused;
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assign sys_reset_n = por_counter[15];
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assign ft601_chip_reset_n = sys_reset_n;
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assign ft601_wakeup_n = 1'b1;
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assign ft601_gpio0 = hb_counter[24];
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assign ft601_gpio1 = sys_reset_n;
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always @(posedge ft601_clk_in) begin
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if (!sys_reset_n) begin
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por_counter <= por_counter + 1'b1;
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hb_counter <= 32'd0;
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packet_div <= 16'd0;
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stream_control_reg <= 3'b001;
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status_request_reg <= 1'b0;
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range_profile_reg <= 32'd0;
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range_valid_reg <= 1'b0;
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doppler_real_reg <= 16'd0;
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doppler_imag_reg <= 16'd0;
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doppler_valid_reg <= 1'b0;
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cfar_detection_reg <= 1'b0;
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cfar_valid_reg <= 1'b0;
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end else begin
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hb_counter <= hb_counter + 1'b1;
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packet_div <= packet_div + 1'b1;
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status_request_reg <= 1'b0;
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range_valid_reg <= 1'b0;
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doppler_valid_reg <= 1'b0;
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cfar_valid_reg <= 1'b0;
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if (cmd_valid) begin
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case (cmd_opcode)
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8'h04: stream_control_reg <= cmd_value[2:0];
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8'hFF: status_request_reg <= 1'b1;
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default: ;
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endcase
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end
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if (packet_div == 16'hFFFF && stream_control_reg[0]) begin
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range_profile_reg <= {hb_counter[31:16], hb_counter[15:0] ^ 16'hA5A5};
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range_valid_reg <= 1'b1;
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if (stream_control_reg[1]) begin
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doppler_real_reg <= hb_counter[31:16];
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doppler_imag_reg <= hb_counter[15:0];
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doppler_valid_reg <= 1'b1;
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end
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if (stream_control_reg[2]) begin
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cfar_detection_reg <= hb_counter[10];
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cfar_valid_reg <= 1'b1;
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end
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end
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end
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end
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usb_data_interface usb_inst (
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.clk(ft601_clk_in),
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.reset_n(sys_reset_n),
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.ft601_reset_n(sys_reset_n),
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.range_profile(range_profile_reg),
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.range_valid(range_valid_reg),
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.doppler_real(doppler_real_reg),
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.doppler_imag(doppler_imag_reg),
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.doppler_valid(doppler_valid_reg),
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.cfar_detection(cfar_detection_reg),
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.cfar_valid(cfar_valid_reg),
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.ft601_data(ft601_data),
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.ft601_be(ft601_be),
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.ft601_txe_n(ft601_txe_n_unused),
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.ft601_rxf_n(ft601_rxf_n_unused),
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.ft601_txe(ft601_txe),
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.ft601_rxf(ft601_rxf),
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.ft601_wr_n(ft601_wr_n),
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.ft601_rd_n(ft601_rd_n),
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.ft601_oe_n(ft601_oe_n),
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.ft601_siwu_n(ft601_siwu_n),
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.ft601_srb(2'b00),
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.ft601_swb(2'b00),
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.ft601_clk_out(ft601_clk_out_unused),
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.ft601_clk_in(ft601_clk_in),
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.cmd_data(cmd_data),
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.cmd_valid(cmd_valid),
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.cmd_opcode(cmd_opcode),
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.cmd_addr(cmd_addr),
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.cmd_value(cmd_value),
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.stream_control(stream_control_reg),
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.status_request(status_request_reg),
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.status_cfar_threshold(16'h1234),
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.status_stream_ctrl(stream_control_reg),
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.status_radar_mode(2'b00),
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.status_long_chirp(16'd3000),
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.status_long_listen(16'd13700),
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.status_guard(16'd17540),
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.status_short_chirp(16'd50),
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.status_short_listen(16'd17450),
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.status_chirps_per_elev(6'd32),
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.status_range_mode(2'b01),
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.status_self_test_flags(5'b11111),
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.status_self_test_detail(8'hA5),
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.status_self_test_busy(1'b0)
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);
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endmodule
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@@ -0,0 +1,57 @@
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# build_te0713_umft601x_dev.tcl
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#
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# Vivado batch build for Trenz TE0713/TE0701 with UMFT601X-B over FMC LPC.
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set script_dir [file dirname [file normalize [info script]]]
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set project_root [file normalize [file join $script_dir ".."]]
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set project_name "aeris10_te0713_umft601x_dev"
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set build_dir [file join $project_root "vivado_te0713_umft601x_dev"]
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set reports_dir [file join $build_dir "reports"]
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set top_file [file join $project_root "radar_system_top_te0713_umft601x_dev.v"]
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set usb_file [file join $project_root "usb_data_interface.v"]
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set xdc_file [file join $project_root "constraints" "te0713_te0701_umft601x.xdc"]
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file mkdir $build_dir
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file mkdir $reports_dir
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create_project -force $project_name $build_dir -part xc7a200tfbg484-2
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set_property target_language Verilog [current_project]
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add_files -norecurse $top_file
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add_files -norecurse $usb_file
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add_files -fileset constrs_1 -norecurse $xdc_file
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set_property top radar_system_top_te0713_umft601x_dev [current_fileset]
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update_compile_order -fileset sources_1
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# Use Performance_ExplorePostRoutePhysOpt strategy for timing closure
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set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]
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puts "INFO: Launching implementation to bitstream (Performance_ExplorePostRoutePhysOpt)..."
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launch_runs impl_1 -to_step write_bitstream -jobs 8
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wait_on_run impl_1
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set impl_status [get_property STATUS [get_runs impl_1]]
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puts "INFO: impl_1 status: $impl_status"
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if {![string match "*Complete*" $impl_status]} {
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error "Implementation did not complete successfully. Status: $impl_status"
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}
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open_run impl_1
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report_clocks -file [file join $reports_dir "clocks.rpt"]
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report_clock_interaction -file [file join $reports_dir "clock_interaction.rpt"]
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report_timing_summary -report_unconstrained -max_paths 100 -file [file join $reports_dir "timing_summary.rpt"]
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report_cdc -details -file [file join $reports_dir "cdc.rpt"]
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report_exceptions -file [file join $reports_dir "exceptions.rpt"]
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report_drc -file [file join $reports_dir "drc.rpt"]
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report_utilization -file [file join $reports_dir "utilization.rpt"]
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set bit_file [get_property BITSTREAM.FILE [current_design]]
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puts "INFO: Build complete."
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puts "INFO: Bitstream: $bit_file"
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puts "INFO: Reports: $reports_dir"
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