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Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

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- Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches,
  and XDC (uncomment be[2:3] pin assignments B21/A21)
- Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline
  warmup and sample skip for DSP48E1 quadrature test
- All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)
This commit is contained in:
Jason
2026-03-16 23:17:38 +02:00
parent af1af3bb91
commit 49eb6169b6
7 changed files with 35 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/tb/tb_nco_xsim.v
+17 -9
View File
@@ -86,8 +86,8 @@ module tb_nco_xsim;
// ════════════════════════════════════════════════════════
$display("--- Test Group 1: Reset Behaviour ---");
#50;
check(cos_out === 16'sd0 || cos_out === 16'sd1,
"cos_out near zero during reset");
check(cos_out === 16'sh7FFF,
"cos_out = 0x7FFF during reset");
check(output_valid === 1'b0, "output_valid = 0 during reset");
// ════════════════════════════════════════════════════════
@@ -184,26 +184,34 @@ module tb_nco_xsim;
#50;
phase_increment = 32'h4CCCCCCD;
reset_n = 1;
repeat (15) @(posedge clk);
// Allow 25 cycles for pipeline flush (DSP48E1 has 6–7 stage latency)
repeat (25) @(posedge clk);
begin : quad_test
reg [63:0] mag_sq;
reg [63:0] mag_min, mag_max;
integer sample_count;
integer skip;
mag_min = 64'hFFFFFFFFFFFFFFFF;
mag_max = 0;
sample_count = 0;
skip = 0;
for (i = 0; i < 200; i = i + 1) begin
@(posedge clk); #0.1;
if (output_valid) begin
// cos^2 + sin^2
mag_sq = cos_out * cos_out + sin_out * sin_out;
if (mag_sq > 0) begin // skip zeros during pipeline fill
if (mag_sq < mag_min) mag_min = mag_sq;
if (mag_sq > mag_max) mag_max = mag_sq;
sample_count = sample_count + 1;
// Skip first 4 valid samples (pipeline settling)
if (skip < 4) begin
skip = skip + 1;
end else begin
// cos^2 + sin^2
mag_sq = cos_out * cos_out + sin_out * sin_out;
if (mag_sq > 0) begin // skip zeros during pipeline fill
if (mag_sq < mag_min) mag_min = mag_sq;
if (mag_sq > mag_max) mag_max = mag_sq;
sample_count = sample_count + 1;
end
end
end
end
9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v
+5 -5
View File
@@ -30,7 +30,7 @@ module tb_usb_data_interface;
// FT601 interface
wire [31:0] ft601_data;
wire [1:0] ft601_be;
wire [3:0] ft601_be;
wire ft601_txe_n;
wire ft601_rxf_n;
reg ft601_txe;
@@ -271,8 +271,8 @@ module tb_usb_data_interface;
check(ft601_wr_n === 1'b0,
"Write strobe active during range data");
check(ft601_be === 2'b11,
"Byte enable=11 for range data");
check(ft601_be === 4'b1111,
"Byte enable=1111 for range data");
// Wait for all 4 range words to complete
wait_for_state(S_SEND_DOPPLER, 50);
@@ -307,8 +307,8 @@ module tb_usb_data_interface;
check(uut.ft601_data_out[7:0] === 8'hAA,
"Header byte 0xAA on data bus");
check(ft601_be === 2'b01,
"Byte enable=01 for header (lower byte only)");
check(ft601_be === 4'b0001,
"Byte enable=0001 for header (lower byte only)");
check(ft601_wr_n === 1'b0,
"Write strobe active during header");
check(uut.ft601_data_oe === 1'b1,