Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

- Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches,
  and XDC (uncomment be[2:3] pin assignments B21/A21)
- Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline
  warmup and sample skip for DSP48E1 quadrature test
- All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)

9_Firmware/9_2_FPGA/constraints/README.md

@@ -43,7 +43,7 @@ own constraint file. Both files constrain the same RTL top module (`radar_system
 |--------|-------------------|---------------------|
 | FT601 USB | Unwired (chip placed, no nets) | Fully wired, Bank 16 |
 | `dac_clk` | Not connected (DAC clocked by AD9523 directly) | Routed, FPGA drives DAC |
-| `ft601_be` width | `[1:0]` in RTL | `[3:0]` needed (RTL update required) |
+| `ft601_be` width | `[1:0]` in upstream RTL | `[3:0]` (RTL updated) |
 | ADC LVDS standard | LVDS_33 (3.3V bank) | LVDS_25 (2.5V bank, better quality) |
 | Status/debug outputs | No physical pins (commented out) | All routed to Banks 35 + 13 |