Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)

Bug #11: platform_noos_stm32.c used HAL_SPI_Transmit instead of
HAL_SPI_TransmitReceive — reads returned garbage. Changed to in-place
full-duplex. Dead code (never called), fixed per audit recommendation.
Test added: test_bug11_platform_spi_transmit_only.c. Mock infrastructure
updated with SPI spy types. All 11 firmware tests pass.

FPGA B2: Migrated long_chirp_lut[0:3599] from ~700 lines of hardcoded
assignments to BRAM with (* ram_style = "block" *) attribute and
$readmemh("long_chirp_lut.mem"). Added sync-only read block for proper
BRAM inference. 1-cycle read latency introduced. short_chirp_lut left
as distributed RAM (60 entries, too small for BRAM).

FPGA B3: Added BREG (window_val_reg) and MREG (mult_i_raw/mult_q_raw)
pipeline stages to doppler_processor.v. Eliminates DPIP-1 and DPOP-2
DRC warnings. S_LOAD_FFT retimed: fft_input_valid starts at sub=2,
+1 cycle total latency. BREG primed in S_PRE_READ at no extra cost.
Both FPGA files compile clean with Icarus Verilog.
This commit is contained in:
Jason
2026-03-19 10:31:16 +02:00
parent 3b32f67087
commit 49c9aa28ad
9 changed files with 3834 additions and 539 deletions
@@ -0,0 +1,15 @@
/* shims/platform_noos_stm32.h -- redirect to mock HAL */
#ifndef SHIM_PLATFORM_NOOS_STM32_H
#define SHIM_PLATFORM_NOOS_STM32_H
#include "stm32_hal_mock.h"
/* Re-export real function prototypes */
int32_t platform_spi_init(void **desc, uint32_t max_speed_hz, uint8_t mode);
int32_t platform_spi_write_and_read(void *desc, uint8_t *data, uint16_t len);
int32_t platform_spi_remove(void *desc);
int32_t platform_gpio_init(void *gpio_desc, uint8_t port_pin, bool is_output);
int32_t platform_gpio_direction_output(void *gpio_desc, uint8_t port_pin, uint8_t value);
int32_t platform_gpio_set_value(void *gpio_desc, uint8_t port_pin, uint8_t value);
int32_t platform_gpio_remove(void *gpio_desc);
void platform_delay_ms(uint32_t ms);
#endif