Wire self-test results (0x31) to USB status readback path, add fpga_self_test to regression
- usb_data_interface.v: Add 3 self-test status inputs, expand status packet
from 7 words (header + 5 data + footer) to 8 words (header + 6 data + footer).
New status_words[5] carries {busy, detail[7:0], flags[4:0]}.
- radar_system_top.v: Wire self_test_flags_latched, self_test_detail_latched,
self_test_busy to usb_data_interface ports. Add opcode 0x31 as status
readback alias so host can read self-test results.
- tb_usb_data_interface.v: Add self-test port connections, verify word 5 in
Group 16, add Group 18 (busy flag + partial failure variant). 81 checks pass.
- run_regression.sh: Add fpga_self_test.v to PROD_RTL lint list and system-
level compile lists. Add tb_fpga_self_test as Phase 1 unit test.
- 24/24 regression tests pass, lint clean (0 errors, 4 advisory warnings).
This commit is contained in:
Jason
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@@ -74,6 +74,11 @@ module tb_usb_data_interface;
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reg [5:0] status_chirps_per_elev;
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reg [1:0] status_range_mode;
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// Self-test status readback inputs
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reg [4:0] status_self_test_flags;
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reg [7:0] status_self_test_detail;
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reg status_self_test_busy;
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// ── Clock generators (asynchronous) ────────────────────────
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always #(CLK_PERIOD / 2) clk = ~clk;
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always #(FT_CLK_PERIOD / 2) ft601_clk_in = ~ft601_clk_in;
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@@ -124,7 +129,12 @@ module tb_usb_data_interface;
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.status_short_chirp (status_short_chirp),
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.status_short_listen (status_short_listen),
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.status_chirps_per_elev(status_chirps_per_elev),
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.status_range_mode (status_range_mode)
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.status_range_mode (status_range_mode),
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// Self-test status readback
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.status_self_test_flags (status_self_test_flags),
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.status_self_test_detail(status_self_test_detail),
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.status_self_test_busy (status_self_test_busy)
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);
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// ── Test bookkeeping ───────────────────────────────────────
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@@ -181,6 +191,9 @@ module tb_usb_data_interface;
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status_short_listen = 16'd17450;
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status_chirps_per_elev = 6'd32;
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status_range_mode = 2'b00;
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status_self_test_flags = 5'b00000;
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status_self_test_detail = 8'd0;
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status_self_test_busy = 1'b0;
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repeat (6) @(posedge ft601_clk_in);
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reset_n = 1;
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// Wait enough cycles for stream_control CDC to propagate
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@@ -867,7 +880,7 @@ module tb_usb_data_interface;
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// ════════════════════════════════════════════════════════
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// TEST GROUP 16: Status Readback (Gap 2)
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// Verify that pulsing status_request triggers a 7-word
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// Verify that pulsing status_request triggers an 8-word
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// status response via the SEND_STATUS state.
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 16: Status Readback (Gap 2) ---");
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@@ -885,6 +898,10 @@ module tb_usb_data_interface;
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status_short_listen = 16'd17450;
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status_chirps_per_elev = 6'd32;
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status_range_mode = 2'b10; // Long-range for status test
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// Self-test status: all 5 tests passed, detail=0xA5, not busy
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status_self_test_flags = 5'b11111;
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status_self_test_detail = 8'hA5;
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status_self_test_busy = 1'b0;
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// Pulse status_request (1 cycle in clk domain — toggles status_req_toggle_100m)
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@(posedge clk);
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@@ -903,14 +920,14 @@ module tb_usb_data_interface;
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check(uut.current_state === S_SEND_STATUS,
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"Status readback: FSM entered SEND_STATUS");
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// The SEND_STATUS state sends 7 words (idx 0-6):
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// idx 0: 0xBB header, idx 1-5: status_words[0-4], idx 6: 0x55 footer
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// After idx 6 it transitions to WAIT_ACK -> IDLE.
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// Since ft601_txe=0, all 7 words should stream without stall.
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// The SEND_STATUS state sends 8 words (idx 0-7):
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// idx 0: 0xBB header, idx 1-6: status_words[0-5], idx 7: 0x55 footer
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// After idx 7 it transitions to WAIT_ACK -> IDLE.
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// Since ft601_txe=0, all 8 words should stream without stall.
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wait_for_state(S_IDLE, 100);
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#1;
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check(uut.current_state === S_IDLE,
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"Status readback: returned to IDLE after 7-word response");
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"Status readback: returned to IDLE after 8-word response");
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// Verify the status snapshot was captured correctly.
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// status_words[0] = {0xFF, 3'b000, mode[1:0], 5'b0, stream_ctrl[2:0], cfar_threshold[15:0]}
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@@ -943,6 +960,10 @@ module tb_usb_data_interface;
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"Status readback: word 3 = {short_listen, 0, chirps_per_elev}");
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check(uut.status_words[4] === {30'd0, 2'b10},
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"Status readback: word 4 = range_mode=2'b10");
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// status_words[5] = {7'd0, busy, 8'd0, detail[7:0], 3'd0, flags[4:0]}
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// = {7'd0, 1'b0, 8'd0, 8'hA5, 3'd0, 5'b11111}
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check(uut.status_words[5] === {7'd0, 1'b0, 8'd0, 8'hA5, 3'd0, 5'b11111},
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"Status readback: word 5 = self-test {busy=0, detail=A5, flags=1F}");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 17: New Chirp Timing Opcodes (Gap 2)
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@@ -999,6 +1020,41 @@ module tb_usb_data_interface;
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check(cmd_opcode === 8'hFF,
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"Chirp opcode: 0xFF (status request)");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 18: Self-Test Readback Variants
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// Verify self-test busy flag, partial failures, and
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// alternate status word 5 values.
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 18: Self-Test Readback Variants ---");
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apply_reset;
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ft601_txe = 0;
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// Scenario A: Self-test busy, partial failure, different detail
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status_self_test_flags = 5'b10110; // T0 fail, T3 fail
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status_self_test_detail = 8'h42;
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status_self_test_busy = 1'b1;
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// Trigger status readback
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@(posedge clk);
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status_request = 1;
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@(posedge clk);
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status_request = 0;
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repeat (8) @(posedge ft601_clk_in); #1;
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wait_for_state(S_SEND_STATUS, 20);
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#1;
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check(uut.current_state === S_SEND_STATUS,
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"Self-test readback A: FSM entered SEND_STATUS");
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wait_for_state(S_IDLE, 100);
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#1;
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check(uut.current_state === S_IDLE,
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"Self-test readback A: returned to IDLE");
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// Verify word 5: {7'd0, busy=1, 8'd0, detail=0x42, 3'd0, flags=5'b10110}
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check(uut.status_words[5] === {7'd0, 1'b1, 8'd0, 8'h42, 3'd0, 5'b10110},
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"Self-test readback A: word 5 = {busy=1, detail=42, flags=16}");
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// ════════════════════════════════════════════════════════
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// Summary
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// ════════════════════════════════════════════════════════
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